Integrated Circuit Debug Port for PCIe Interface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging integrated circuit designs using high-speed interfaces like PCIe requires substantial modifications to the user design, including adding debug traffic circuitry and modifying register-transfer level (RTL) designs, which can be cumbersome and time-consuming.
Innovation Solution
Incorporating a dedicated debug port in high-speed serial interface circuitry, such as PCIe, that allows for direct access to debug circuitry without altering the underlying RTL design, enabling debugging signals to be transmitted through a dedicated debug function block and DMA controller, facilitating debugging without modifying the user design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCIe interface is used for debugging, then debugging speed is improved, but device complexity increases due to required modifications
Solution Approach 1:
The patent extracts the debug traffic circuitry from the user design and places it in the domain layer as separate, dedicated components (debug multiplexer, debug demultiplexer, debug address register). This allows PCIe debugging functionality to be added without modifying the underlying RTL design, thus improving debugging speed while minimizing design complexity changes.
Solution Approach 2:
The patent segments the debug functionality into distinct modular components: debug multiplexer for selecting between user and debug traffic, debug demultiplexer for separating debug responses, and debug address register for managing address space. This segmentation allows independent implementation and configuration of debug features without affecting the main design.
2Adaptability or versatility
If debug traffic circuitry is added to enable PCIe debugging, then debugging capability is improved, but ease of manufacture deteriorates due to additional circuitry
Solution Approach 1:
The patent implements universal debug components that can work with any user design. The debug multiplexer and demultiplexer are generic interfaces that handle both user traffic and debug traffic through standardized protocols, making the debugging capability universally applicable without requiring design-specific custom circuitry.
Solution Approach 2:
The patent introduces intermediary components (debug multiplexer, debug demultiplexer, domain layer) that mediate between the PCIe interface and the user design. These intermediaries handle all debug-related operations without requiring direct integration into the user's RTL code, thus improving adaptability while maintaining ease of manufacture.
3Ease of operation
If Base Address Register is expanded or additional BAR is added for debug logic, then debugging access is improved, but device complexity increases
Solution Approach 1:
The patent implements a dedicated debug address register that provides partial address space allocation specifically for debug operations. Instead of requiring full expansion of the address space or addition of complex BAR configurations, the debug address register provides sufficient addressing capability for debug purposes with minimal overhead.
Data Source
AI summary
An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit.