Integrated Circuit Post-Silicon Debug via Software Prototype
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Solution Overview
Problem
The increasing complexity of microprocessors and SoC designs has led to a significant increase in the time and resources required for design verification and debugging, particularly in post-silicon stages where limited observability of signal values and partial data availability make debugging hardware lab issues challenging and time-consuming.
Innovation Solution
A system and method that generates a software design prototype and a lab All-Event-Trace (AET) normalized model of the integrated circuit, allowing for the creation of a lab scenario and replayed AET to debug hardware issues by transforming hardware information into a tristate logical simulation, increasing observability and efficiency in post-silicon hardware debug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-silicon hardware debugging is performed using traditional methods with limited observability, then hardware issues can be identified, but the time and resources required for debugging increase significantly
Solution Approach 1:
The patent creates a software design prototype that copies and emulates the hardware circuit behavior. This virtual model allows complete observability and control without accessing the physical hardware, enabling rapid debugging without time-consuming physical access requirements.
Solution Approach 2:
The patent introduces a software design prototype as an intermediary between the hardware under test and the debugger. This prototype layer provides full observability and control capabilities, mediating the interaction and eliminating the need for direct hardware access.
2Measurement precision
If hardware information is transformed into a lab AET normalized model, then observability of signals is improved, but the complexity of the verification process increases
Solution Approach 1:
The patent creates a normalized model that copies only the essential functional behavior of the hardware, filtering out non-functional aspects. This selective copying maintains signal observability while reducing the complexity burden on the verification process.
Solution Approach 2:
The patent extracts and separates functional behavior from non-functional aspects of the hardware design. By taking out only the essential functional elements needed for verification, the process reduces complexity while maintaining the necessary observability for debugging.
3Productivity
If pre-silicon verification uses automated test case generation tools, then functional verification is accomplished, but the time from hardware lab to general availability increases
Solution Approach 1:
The patent performs preliminary creation of the software design prototype during the design phase, before hardware fabrication. This advance preparation enables rapid post-silicon debugging by having the verification model ready, significantly reducing turnaround time when hardware issues arise.
Solution Approach 2:
The patent creates a virtual copy of the hardware behavior that can be instantly deployed for verification. This pre-prepared software prototype eliminates delays in setting up verification environments, enabling rapid iteration and reducing time to general availability.
Data Source
AI summary
A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.