IC Debug Circuit for Multi-Cycle Triggered Signal Capture
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Solution Overview
Problem
Current techniques for debugging integrated circuits, such as clock-stop and scan-dump (CSSD) and real-time monitoring of hard block signals, are limited in capturing internal signal values before, during, and after an event trigger, making it complex and time-consuming to diagnose structural and functional faults.
Innovation Solution
A circuit and method that include a shift register to store data values over multiple cycles, a counter unit to output a trigger signal, and a switch to open connections between input interfaces and registers, allowing for the capture of internal signal values before, during, and after a trigger event, using a pipeline stage with flip-flops and registers to hold and select data values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock-stop and scan-dump technique is used to capture signal values, then signal values can be captured at a particular point in time, but it is not possible to control status information of internal signals after a particular event and additional logic resources are required
Solution Approach 1:
The patent configures flip-flops into scan-registers in advance before the trigger event occurs. This preliminary configuration allows the circuit to be ready to capture signals immediately when the trigger event happens, eliminating the need for additional logic resources during the actual capture moment.
Solution Approach 2:
The patent dynamically switches between functional mode and scan mode using a scan-enable signal. The flip-flops can operate normally during functional mode and be reconfigured into scan-registers when needed, providing both operational flexibility and capture capability without requiring separate dedicated logic resources.
2Speed
If real-time monitoring of hard block signals is used, then real-time signal values can be monitored, but large clock multiplexers are required which add clock insertion delays affecting design performance
Solution Approach 1:
The patent extracts only the necessary signal capture function from the complex real-time monitoring system. By using scan-registers configured from existing flip-flops, it captures signal values without requiring large clock multiplexers, thus avoiding the clock insertion delays that would affect design performance.
Solution Approach 2:
The patent makes the existing flip-flops multi-functional by configuring them into scan-registers when needed. These same flip-flops serve both their original functional purpose and the signal capture purpose, eliminating the need for separate dedicated monitoring logic and reducing overall device complexity.
3Reliability
If scan registers are used to dump FF contents, then structural faults can be addressed, but functional faults and post-silicon debugging are limited
Solution Approach 1:
The patent triggers the scan-enable signal immediately upon detecting a trigger event, capturing signals at the exact moment of the event. This preliminary action at the critical moment enables functional fault debugging by preserving the circuit state when the functional anomaly occurred, not just structural information.
Solution Approach 2:
The patent uses trigger events as feedback from the circuit's operational state to initiate the capture process. When a trigger event occurs, it automatically triggers the scan-enable signal to capture relevant signals, providing feedback-based debugging that adapts to actual circuit behavior and enables functional fault analysis.
Data Source
AI summary
Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.