Integrated Circuit Decoy Transistors for Reverse Engineering Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern microscopic techniques can reveal the architecture of integrated-circuit component assemblies, making it possible to reverse engineer them, which is undesirable for protecting intellectual property and security.
Innovation Solution
Incorporating transistors with gate dielectric regions configured to always be in an off state, using a stack of silicon oxide-nitride-oxide layers, and arranging transistors to deceive observers about the logic function, combined with self-aligned gate spacers to obscure the configuration, ensuring the first transistor remains off at supply voltages up to 2 volts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are configured to always be in an off state using thick gate dielectric regions, then reverse engineering protection is improved, but transistor functionality and circuit operation are worsened
Solution Approach 1:
The integrated circuit is divided into two distinct domains: a first domain with transistors configured to always be off (decoy transistors) and a second domain with normally functional transistors. This segmentation allows the circuit to simultaneously provide reverse engineering protection in the first domain while maintaining operational functionality in the second domain, resolving the contradiction between protection and functionality.
Solution Approach 2:
The decoy transistors in the first domain are designed to visually resemble functional transistors when observed through microscopic techniques, creating a deceptive copy that misleads reverse engineers. These copied transistor structures include gate regions and gate dielectric regions that mimic the appearance of operational transistors, but are configured with thick gate dielectrics to ensure they remain permanently off, thus providing protection while maintaining the illusion of functionality.
2Reliability
If gate dielectric thickness is increased to ensure transistors remain off, then protection against reverse engineering is improved, but manufacturing precision requirements are worsened
Solution Approach 1:
The gate dielectric thickness parameter is deliberately changed to a specific range (greater than 4 nm and preferably at least 10 nm) that ensures transistors remain permanently off at supply voltages up to 2 volts. This parameter change provides a clear manufacturing target that guarantees the off-state condition while being achievable with standard fabrication processes, thus resolving the contradiction between reliability and manufacturing precision.
3Reliability
If transistors are arranged to deceive observers about logic function, then reverse engineering protection is improved, but device complexity is worsened
Solution Approach 1:
The circuit arrangement is inverted in the sense that the apparent logic function derived from transistor arrangement does not match the actual operational logic function. The decoy transistors are positioned and configured to suggest a particular logic function when observed, but their permanent off-state configuration means they do not actually contribute to that logic function, creating an inverted relationship between appearance and reality that effectively protects against reverse engineering.
Data Source
AI summary
An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.