Integrated Circuit Defect Identification Using Data Fusion
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Solution Overview
Problem
Conventional high-throughput optical inspection systems lack resolution to detect defects in integrated circuits, while high-resolution electron beam systems have low throughput, making them unsuitable for inline defect inspection due to long scanning times and high false positive/negative rates in die-to-die and die-to-database techniques.
Innovation Solution
The D3D method and system use data fusion, decision tree, and boosting techniques to generate feature data from input patterns, integrating defect detection results to achieve high sensitivity and specificity, reducing the need for high-resolution images and improving inspection efficiency by focusing on 'care areas' with potential defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional high-throughput optical inspection systems are used, then productivity is improved, but measurement precision deteriorates due to insufficient resolution
Solution Approach 1:
The inspection system segments the wafer into multiple regions of interest (ROIs) or 'care areas' based on process conditions and defect probabilities. Instead of inspecting the entire wafer at high resolution, only selected regions are subjected to detailed examination, thereby maintaining high throughput while improving defect detection capability in critical areas.
Solution Approach 2:
The system applies different inspection strategies to different regions of the wafer. High-resolution inspection is applied locally to identified care areas where defects are most likely to occur or where process variations are greatest, while other regions receive standard or reduced inspection, optimizing the balance between productivity and measurement precision.
2Measurement precision
If high-resolution electron beam systems are used, then measurement precision is improved, but productivity deteriorates due to low throughput
Solution Approach 1:
The wafer inspection is segmented into multiple passes and regions. Electron beam inspection is applied only to specific care areas identified in earlier stages, rather than scanning the entire wafer. This segmentation enables high-resolution inspection to be performed on limited regions, improving throughput while maintaining measurement precision.
Solution Approach 2:
The system performs preliminary optical inspection and process condition analysis before applying electron beam inspection. Regions are pre-identified as care areas based on process parameters and initial screening, so that the high-resolution electron beam system only needs to inspect predetermined regions, significantly reducing total inspection time while maintaining high defect detection capability.
3Measurement precision
If die-to-die or die-to-database techniques are used, then measurement precision is improved, but reliability deteriorates due to high false positive and negative rates
Solution Approach 1:
The system introduces process condition data and multiple defect detection techniques as intermediaries between the raw inspection data and final defect identification. By analyzing process conditions and combining results from multiple detection methods, the system reduces false positives and negatives, improving the reliability of defect identification while maintaining measurement precision.
Solution Approach 2:
The defect detection system uses a composite approach combining multiple defect detection techniques (e.g., optical inspection, electron beam inspection, process condition analysis) rather than relying on a single method. This multi-technique composite strategy cross-validates findings and reduces false indications, thereby improving the reliability of defect identification while maintaining high detection accuracy.
Data Source
AI summary
Methods and systems for identifying defects in an integrated circuit are provided. The method includes receiving input data of a pattern associated with an integrated circuit, determining feature data associated with features of the pattern using the input data, determining defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determining a defect identification result using the defect detection results. The system includes a processor and a memory. The memory is coupled to the processor and configured to store a set of instructions to receive input data of a pattern associated with an integrated circuit, determine feature data associated with features of the pattern using the input data, determine defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determine a defect identification result using the defect detection results.