Integrated Circuit Defect Identification Using Multi-Scheme Scoring

The patent segments the fault ranking process into multiple independent scoring schemes (per-fail, per-cycle, per-sequence) that evaluate different aspects of fault behavior. Each scoring scheme independently ranks fault candidates based on specific criteria, and the final ranking is determined by comparing results across all schemes. This segmentation allows comprehensive evaluation without sacrificing processing efficiency, as each scheme can be computed independently and parallelized.

The patent merges multiple scoring scheme results through a comparison mechanism that integrates rankings from per-fail, per-cycle, and per-sequence analyses. By combining these diverse evaluation perspectives, the system achieves more accurate fault location identification while maintaining computational efficiency through systematic integration of results rather than exhaustive re-simulation.

The patent applies periodic action by implementing multiple passes over the fault candidate data, where each pass applies heuristic algorithms under different scoring schemes and criteria. Rather than a single pass, the system iteratively refines defect identification by re-evaluating candidates with updated information from each scoring scheme, thereby reducing false positives while maintaining computational feasibility through structured repetition.

The patent incorporates feedback mechanisms where results from each scoring scheme and pass are fed back into the subsequent evaluation stages. Fault candidates that initially appear as false positives can be re-evaluated with feedback from multiple scoring perspectives, allowing the system to correct earlier misidentifications and improve overall reliability without requiring complete re-computation from scratch.

The patent makes the defect identification system universal by designing scoring schemes that can handle both partitioned and overlapping defect scenarios within a unified framework. The per-fail, per-cycle, and per-sequence scoring mechanisms are capable of evaluating faults regardless of whether they belong to separate clusters or overlap, eliminating the need for pre-processing partitioning steps and directly addressing failures in their original context.

The patent introduces scoring schemes as intermediaries that mediate between raw failure data and final defect identification. Rather than directly partitioning failures based on circuit topology, the scoring schemes act as intermediaries that evaluate all potential defect locations against multiple criteria, naturally handling overlapping defects by comparing their explanatory power across different failure patterns without requiring explicit partitioning decisions.

The patent applies partial action by evaluating only the most promising fault candidate combinations rather than simulating all possible combinations. The scoring schemes identify and prioritize candidate defects based on their individual explanatory power, then focus computational resources on evaluating combinations of top-ranked candidates. This selective approach achieves sufficient accuracy for multiple defect detection while avoiding the exponential time cost of exhaustive simulation.

The patent performs preliminary action by using scoring schemes to pre-evaluate and rank individual fault candidates before combining them into multi-defect scenarios. This preliminary ranking identifies the most likely defect locations based on single-fault analysis, allowing the system to then efficiently evaluate only combinations involving these high-probability candidates rather than all possible combinations, significantly reducing simulation time while maintaining detection accuracy.