Integrated Circuit Degradation Modeling via Mechanism Interaction
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Solution Overview
Problem
Conventional transistor models fail to accurately estimate transistor degradation due to the interaction between different degradation mechanisms, such as channel hot carriers (CHC) and biased temperature instability (BTI), leading to over- or under-estimation of CHC degradation, which affects integrated circuit reliability and performance.
Innovation Solution
The method involves modeling and fabricating integrated circuits by accounting for interactions between multiple degradation mechanisms, specifically using measurements of BTI-induced changes to refine CHC models, thereby improving estimates of CHC lifetimes and adjusting design and process parameters to compensate for degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate modeling of CHC, NBTI, and PBTI degradation mechanisms is used, then modeling simplicity is maintained, but total degradation estimation accuracy deteriorates due to ignoring interactions between mechanisms
Solution Approach 1:
The patent combines separate degradation mechanism models (CHC, NBTI, PBTI) into an integrated model that accounts for their interactions. The total degradation is calculated by considering how these mechanisms affect each other, rather than simply summing independent degradation amounts, thereby improving estimation accuracy while maintaining manageable complexity.
2Productivity
If conventional transistor models are used, then design process speed is maintained, but reliability estimation accuracy deteriorates due to over- or under-estimation of CHC degradation
Solution Approach 1:
The patent applies degradation mechanism interactions in the modeling and design stages before actual device fabrication and testing. By incorporating interaction effects into the preliminary design models, the patent enables more accurate reliability predictions without requiring iterative redesigns or extensive post-fabrication testing, thus maintaining design process efficiency.
3Reliability
If design parameters are increased to compensate for degradation uncertainty, then reliability is improved, but device packing density deteriorates due to over-conservatism
Solution Approach 1:
The patent uses accurate degradation modeling to determine precise parameter adjustments needed for reliability compensation. Instead of applying conservative over-design margins, the model calculates the exact parameter changes required based on predicted degradation, allowing for more aggressive and efficient design optimization that maintains reliability while improving packing density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides more accurate estimates of transistor degradation, leading to improved integrated circuit reliability and performance by reducing over-conservatism in design and increasing packing density without compromising reliability.
Implementation Method 1
Hot carriers, those with very high kinetic energy, can then generate electron-hole pairs near the drain due to impact ionization from atomic-level collisions
Implementation Method 2
can be injected into the gate channel interface, breaking Si—H bonds and increasing interface trap density
Implementation Method 3
negative biased temperature instability (NBTI) degradation, which affects primarily P-channel MOS transistors, in which a stress voltage causes the generation of interface traps (NIT) between the gate dielectric and a semiconducting substrate
Implementation Method 4
positive biased temperature instability (PBTI) degradation, in which a stress voltage causes the generation of bulk electron trapping in the gate dielectric
Data Source
AI summary
An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).