IC Delay Circuit Layout Using Active Region Width Variation
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in efficiently delaying signals to meet timing and operational requirements, particularly due to limitations in delay circuit design and implementation.
Innovation Solution
The proposed solution involves designing delay circuits within IC devices that incorporate N-type and P-type transistors over continuous and discontinuous active regions, along with specific configurations of output connectors and via structures to enhance delay and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional delay circuits are used in IC devices, then the circuit can function with standard design, but the delay efficiency and timing performance are insufficient
Solution Approach 1:
The patent applies local quality by creating discontinuous active regions with varying widths under different transistor regions. Specifically, the active region has a first width under the first transistor and a second width under the second transistor, where the widths differ to optimize delay characteristics locally. This allows different portions of the circuit to have tailored delay properties, improving overall timing performance without uniformly increasing complexity throughout the entire circuit.
Solution Approach 2:
The patent employs parameter changes by modifying the physical dimensions of active regions to control delay characteristics. The active region width is varied (first width vs. second width) to adjust the electrical parameters of transistors, thereby changing the delay time of signal propagation through the delay circuit. This enables precise control over timing characteristics to meet specific design requirements.
2Loss of time
If delay circuits are designed to increase delay time, then timing requirements can be met, but chip area increases
Solution Approach 1:
The patent applies segmentation by dividing the active region into discontinuous segments with different widths. Instead of using a single large continuous active region that would increase chip area, the design segments the active region into multiple portions (first active region portion and second active region portion) with optimized local widths. This segmentation achieves the required delay time through distributed optimization rather than uniform expansion, thereby reducing overall chip area consumption.
3Ease of manufacture
If standard cell libraries and EDA tools are used for design, then design process is streamlined, but delay circuit performance optimization is limited
Solution Approach 1:
The patent reconciles ease of manufacture with manufacturing precision by implementing local quality variations within the standard cell framework. The discontinuous active regions with different widths can be defined using standard EDA tool flows and cell library approaches, maintaining design efficiency. Simultaneously, the local width variations provide precise control over transistor characteristics and delay timing, achieving high manufacturing precision without sacrificing the benefits of standardized design processes.
Data Source
AI summary
An integrated circuit (IC) device includes at least one circuit having an input and an output, and an output connector electrically coupled to the output. The circuit further includes a plurality of transistors electrically coupled with each other between the input and the output. The output is in a first metal layer. The output connector includes a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. The second conductive pattern electrically couples the output to the first conductive pattern.