Integrated Circuit Delay Measurement and Dynamic Path Reconfiguration
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Solution Overview
Problem
As semiconductor integrated circuits scale down, manufacturing defects and process variations lead to unpredictable signal propagation delays, and performance degradation over time, making it challenging to maintain consistent circuit functionality, especially in programmable logic devices (PLDs) where function mapping is dynamic.
Innovation Solution
A method for accurately measuring propagation delay between signal nodes in integrated circuits using a flexible on-chip clock generator and a built-in-self-test circuit, which steps through frequencies to detect timing failures, constructing a cumulative histogram to derive path delay while minimizing clock jitter errors, allowing for dynamic re-mapping of circuit paths to maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature sizes are decreased to improve technology scaling, then integration density is improved, but manufacturing precision deteriorates due to increased process variation
Solution Approach 1:
The patent applies preliminary action by measuring and characterizing process variations and delay characteristics during manufacturing before the circuit is deployed. This allows the system to pre-compensate for manufacturing variations by storing multiple configuration bitstreams corresponding to different process conditions, enabling the circuit to adapt to the specific manufacturing variations of each device.
Solution Approach 2:
The patent employs parameter changes by varying configuration parameters (mapping of logic functions to physical resources) based on measured process variations. The system changes the operational parameters of the circuit by selecting different configuration bitstreams that optimize performance for the specific process conditions of each manufactured device.
2Area of moving object
If feature sizes are decreased to improve technology scaling, then integration density is improved, but delay variation increases between fast and slow paths
Solution Approach 1:
The patent applies dynamics by making the circuit configuration dynamic rather than fixed. The system can change the mapping of logic functions to physical resources based on measured delay characteristics, allowing the circuit to adapt to varying path delays. This dynamic reconfiguration capability enables the system to maintain reliable operation despite increased delay variation from scaling.
Solution Approach 2:
The patent employs feedback by measuring actual delay characteristics of the circuit and using this information to select appropriate configuration bitstreams. The system continuously monitors performance and adjusts the configuration to compensate for delay variations, creating a closed-loop system that maintains reliability despite manufacturing variations.
3Power
If current density and electrical field strength are increased to maintain performance, then power delivery is improved, but circuit ageing accelerates causing performance degradation
Solution Approach 1:
The patent applies preliminary action by measuring delay characteristics at different stages of circuit operation and preparing multiple configuration bitstreams in advance. This allows the system to proactively compensate for ageing effects before they cause performance degradation, extending the operational lifespan of the circuit by preemptively adjusting the configuration.
Solution Approach 2:
The patent employs self-service by enabling the circuit to automatically monitor its own performance degradation and reconfigure itself without external intervention. The system uses built-in measurement circuits to detect delay increases due to ageing and automatically selects alternative configurations that restore performance, allowing the circuit to service itself throughout its operational life.
4Ease of manufacture
If configuration bitstream generation is performed during manufacturing, then device functionality is defined, but manufacturing time and complexity increase significantly
Solution Approach 1:
The patent applies partial action by performing only the necessary measurements and generating only the required configuration bitstreams during manufacturing, rather than fully characterizing all possible process variations. This selective approach reduces the time and complexity of the manufacturing process while still achieving sufficient compensation for the most significant variations.
Solution Approach 2:
The patent employs parameter changes by using simplified measurement parameters during manufacturing that capture the essential process variations without requiring exhaustive characterization. The system changes the level of detail in measurements and configuration generation to balance manufacturing efficiency with adequate performance compensation.
Data Source
AI summary
A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.