Integrated Circuit Delay Modeling via Common Identifier and Location Qualification
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Solution Overview
Problem
Current integrated circuit design models for programmable logic devices, such as FPGAs, require duplicating components with different delay values, leading to an expensive and complex process of creating new components, definitions, and distributing updated files.
Innovation Solution
A method and apparatus for modeling integrated circuits in a CAD system that allows different delay values for similar configuration blocks by defining a common delay identifier in the device model and qualifying delay values based on location within the component hierarchy, enabling separate storage and management of delay values in a value model.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common delay identifier is used for all component instances, then the device model structure is simplified and easier to maintain, but all component instances must use the same delay value which reduces flexibility
Solution Approach 1:
The patent segments the delay value assignment by separating the common delay identifier (in device model) from the specific delay values (in value model). This allows the device model to remain simple while the value model provides granular control over individual component instances through location-based qualification.
Solution Approach 2:
The patent adds a new dimension to delay value management by introducing location-based qualification. Instead of only having a flat delay value assignment, the system now qualifies delay values based on component instance location in the component hierarchy, enabling both common and specific delay values without increasing device model complexity.
2Adaptability or versatility
If different delay values are required for different component instances, then flexibility is improved, but the process becomes expensive and complex requiring new components and file distributions
Solution Approach 1:
The patent separates the delay value management into two independent files: device model (containing component definitions and common delay identifiers) and value model (containing specific delay values with location qualifications). This segmentation allows different delay values for different instances without creating new components or redistributing the entire device model.
Solution Approach 2:
The patent extracts the delay value assignments from the device model and places them in a separate value model file. This extraction allows delay values to be modified independently without affecting the device model structure, eliminating the need to redistribute definition files when updating delay values.
3Productivity
If delay values are stored in a separate speed file, then updates are easier and faster, but there is no way to assign different delay values to different instances of the same component
Solution Approach 1:
The patent segments the value model into location-qualified delay value entries. Each entry associates a delay value with a specific component instance location in the component hierarchy, allowing the single value model file to serve both purposes: efficient updates and instance-specific assignments.
Solution Approach 2:
The patent adds location-based qualification as a new dimension to the delay value storage structure. This allows the value model to differentiate between component instances using the same delay identifier by specifying their location in the component hierarchy, thereby enabling instance-specific delay values while maintaining the benefits of separate file storage.
Data Source
AI summary
Method, apparatus, and computer readable medium for modeling an integrated circuit in a computer aided design system (CAD) are described. In some examples, a device model of the integrated circuit is generated in at least one first computer file, the device model having a component hierarchy. A common delay identifier is defined for component instances in the component hierarchy of the device model. A value model is generated for the device model in at least one second computer file. Delay values are defined for the common delay identifier in the value model, at least a portion of the delay values being qualified based on location in the component hierarchy of at least one of the component instances.