Integrated Circuit Delay Measurement Using Shift Register and Modulo Counter
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Solution Overview
Problem
Existing methods for measuring signal propagation delays in integrated circuits (ICs) are limited by the need for adjustable delay lines and off-chip measuring equipment, which increase costs and complexity, and struggle to accurately test many delays simultaneously without introducing irrelevant delays or requiring precise clock edges.
Innovation Solution
A circuit using a shift register and asynchronous clocking to measure path delays by applying an alternating signal and sampling logic values, with an analysis circuit that computes delay changes using a modulo counter, allowing simultaneous measurement of rise and fall delays across multiple paths without on-chip adjustable delays or off-chip clock adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If adjustable delay lines and off-chip measuring equipment are used to measure signal propagation delays, then measurement accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the delay measurement function from external test equipment and implements it using only internal on-chip resources. The boundary scan register and on-chip logic elements are used to create a self-contained delay measurement system that eliminates the need for external adjustable delay lines and measuring equipment, while maintaining measurement accuracy through the use of available on-chip timing resources.
Solution Approach 2:
The IC performs delay measurements on itself using its own internal resources. The boundary scan register, output drivers, and logic elements work together to generate test signals and measure delays without requiring external test equipment. The system uses its own clocking and logic structures to accomplish what would traditionally require separate external instruments.
2Productivity
If multiple delays are measured simultaneously using traditional methods, then productivity is improved, but measurement precision deteriorates due to irrelevant delays and clock edge requirements
Solution Approach 1:
The patent segments the delay measurement process into distinct phases using the boundary scan register's shift and parallel output modes. Each logic element's delay is measured independently by controlling when its output is sampled, allowing multiple measurements to proceed without interference from irrelevant delays. The segmented approach isolates each measurement from others occurring simultaneously.
Solution Approach 2:
The system dynamically controls the timing of signal capture by adjusting when parallel output latches are enabled during the shift operation. This dynamic timing control allows the system to capture signals at optimal moments for each individual path being measured, even as multiple measurements occur simultaneously, preventing measurement errors from clock edge misalignment.
Data Source
AI summary
A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits.