Integrated Circuit Design File Segmentation for IP Protection
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Solution Overview
Problem
Current methods for protecting integrated circuit intellectual property during manufacturing are inadequate, as circuit obfuscation techniques can be overcome by adversaries, and human vetting is prone to errors, posing risks to national security and economic stability.
Innovation Solution
The method involves partitioning integrated circuit design files into Front End of Line (FEOL) and Back End of Line (BEOL) sub-circuit files, which are sent to separate foundries for manufacturing on individual substrates, ensuring that no single file contains sufficient information to deduce the overall circuit function, thereby mitigating intellectual property theft.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuit design files are sent to a single foundry for manufacturing, then manufacturing efficiency is improved, but intellectual property theft risk increases
Solution Approach 1:
The integrated circuit design file is segmented into multiple separate layout files, each representing a different layer or portion of the circuit. These segmented files are then distributed to different foundries for manufacturing, so that no single foundry receives the complete circuit design information. This segmentation approach maintains manufacturing efficiency by allowing parallel processing while reducing intellectual property theft risk through information dispersal.
2Reliability
If circuit obfuscation techniques are used to protect intellectual property, then confidentiality is improved, but vulnerability to adversarial attacks increases
Solution Approach 1:
Instead of relying on obfuscation techniques that can be deciphered by determined adversaries, the patent segments the circuit design into multiple layer files and distributes them geographically. This structural segmentation approach provides confidentiality protection that is not vulnerable to analytical attacks, as the complete circuit function cannot be reconstructed without assembling all distributed segments.
3Reliability
If human vetting of staff and facilities is implemented, then security is improved, but errors in vetting process increase risk
Solution Approach 1:
The patent extracts the critical circuit information from the complete design file and retains only essential manufacturing data in each distributed layer file. This extraction approach removes the vulnerability associated with human vetting errors, as the distributed files contain minimal information that would be valuable to adversaries even if obtained through imperfect vetting processes.
Data Source
AI summary
An integrated circuit includes a plurality of vertically-stacked layers including a front end of line (FEOL) layer and a back end of line (BEOL) layer. The FEOL layer includes individual transistors that are not interconnected. The BEOL layer includes transistor interconnections and no transistors. The transistors are electrically connected to the transistor interconnections by vias within the FEOL ad BEOL layers. The FEOL and BEOL layers each have contact pads on the top and bottom surfaces thereof that are each in alignment with vias, are arranged in a checkerboard pattern, and occupy about fifty percent of the surface area of the FEOL and BEOL layers. The contact pads on a top surface of the FEOL layer are in electrical communication with contact pads on a bottom surface of the BEOL layer to facilitate vertical current flow between the transistors and the transistor interconnections through the vias.