Hierarchical Design Flow Generator for IC Timing Predictability
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Solution Overview
Problem
Current hierarchical design flows for integrated circuits (ICs) are limited by their adherence to either top-down or bottom-up methodologies, failing to accommodate staggered design maturity and resulting in inefficiencies such as increased turn-around-time and reduced timing predictability.
Innovation Solution
A mixed methodology is introduced, partitioning the design flow into a late and early portion, allowing simultaneous top-down and bottom-up design by managing timing budgets and modeling blocks to leverage staggered maturity, thereby reducing iterations and improving timing predictability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional hierarchical design flow (top-down or bottom-up) is used, then the design process follows a structured methodology, but the turn-around-time increases and timing predictability decreases due to sequential processing and inability to accommodate staggered design maturity
Solution Approach 1:
The design flow is segmented into multiple portions (early design flow portion and late design flow portion) that can be processed in parallel. This segmentation allows different blocks to progress at different stages simultaneously, accommodating staggered design maturity while improving timing predictability through structured budgeting and modeling at each segment level.
Solution Approach 2:
The design flow is made dynamic by allowing flexible progression through different portions based on block readiness and maturity. Blocks can move through the design flow at different rates, with the ability to iterate locally without requiring full sequential processing, thereby reducing overall turn-around-time while maintaining timing control.
2Productivity
If a traditional hierarchical design flow is used, then the design methodology is well-defined, but unnecessary iterations occur between place-and-route and synthesis stages
Solution Approach 1:
Floor planning and timing budgeting are performed as preliminary actions early in the design flow, establishing constraints and guidelines before place-and-route and synthesis stages. This preliminary structuring prevents unnecessary iterations by ensuring that subsequent stages work within predetermined boundaries, reducing the need for repeated cycles between synthesis and implementation.
3Productivity
If parallel design progress is enabled for blocks at different stages, then turn-around-time is reduced and timing predictability is enhanced, but the complexity of managing multiple design flow portions increases
Solution Approach 1:
Timing budgets and block models serve as intermediaries that coordinate parallel design progress across different portions. These intermediaries provide standardized interfaces and constraints that simplify the management of parallel flows, allowing blocks to progress independently while maintaining overall timing predictability through centralized budgeting and modeling frameworks.
Data Source
AI summary
A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.