IC Design Layout ePatterning Optimization
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Solution Overview
Problem
Current IC design methods face challenges in efficiently integrating cross-team interactions, particularly at smaller feature sizes, due to independent processing modules, reduced design flexibility, and simpler simulation patterns that do not accurately represent real designs, leading to suboptimal chip performance and increased redesign efforts when transferring products between fabrication sites or technologies.
Innovation Solution
The proposed method involves an integrated circuit (IC) design approach that incorporates electrical patterning (ePatterning) modifications based on both electrical and optical parameters, using an ePatterning database to optimize geometrical parameters, eliminate separate optical and electrical simulations, and enhance manufacturing information integration, allowing for multi-object optimization of IC design layouts directly within the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If independent processing modules are used for lithography patterning, thin film deposition, and etching, then each module can operate autonomously, but cross-team interaction is reduced and modeling efficiency is not maximized
Solution Approach 1:
The patent combines multiple independent processing modules (lithography patterning, thin film deposition, etching) into an integrated design flow that maximizes modeling efficiency while maintaining cross-team interaction. The full chip tape is achieved through coordinated modeling of all modules together, resolving the contradiction between autonomous operation and collaborative efficiency.
2Reliability
If statistical corner is added to simulation model for design reference, then design margin is provided, but design flexibility is reduced
Solution Approach 1:
The patent implements a dynamic design flow where statistical corners are applied selectively rather than rigidly. The methodology allows design parameters to be adjusted based on actual process variations and modeling results, providing both design margin through statistical analysis and flexibility through iterative optimization, resolving the contradiction between reliability and adaptability.
3Device complexity
If simpler patterns are used in simulation, then simulation complexity is reduced, but the patterns do not accurately represent frequently designed patterns
Solution Approach 1:
The patent performs preliminary characterization of actual frequently-designed patterns before simulation. By capturing real pattern geometries and characteristics in advance, the simulation can use accurate representative patterns without excessive complexity, resolving the contradiction between simulation simplicity and pattern accuracy.
4Productivity
If feature size is shrunken to 65 nanometers, 45 nanometers, and below, then IC performance is improved, but control of resistance/capacitance, timing, leakage, and topology becomes more challenging
Solution Approach 1:
The patent implements a feedback-driven design flow where modeling results from all processing modules are continuously fed back to optimize design parameters. This closed-loop approach enables effective control of resistance/capacitance, timing, leakage, and topology at advanced feature sizes by using actual process data to guide design adjustments, resolving the contradiction between performance and control complexity.
Data Source
AI summary
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.