Integrated Circuit Design with Real-Time LDE Extraction
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Solution Overview
Problem
Integrated circuit design systems face inefficiencies due to the lack of real-time update of layout-dependent effects (LDEs) during the schematic design phase, reliance on preset design rules, and inability to accurately cross-probe between p-cell symbols and layouts, leading to repeated design iterations and errors.
Innovation Solution
An integrated circuit design system that includes a schematic editor, layout editor, device array design module, and BEOL router and RC extractor to generate and update LDEs in real-time, allowing for accurate pre-layout simulations and seamless connectivity-driven flow between schematic and layout views, independent of system design rule constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If post-layout simulation is performed to account for layout-dependent effects, then accuracy of performance simulation is improved, but design iteration time increases
Solution Approach 1:
The patent applies preliminary action by performing RC extraction and generating RC information during the pre-layout phase, before the actual layout is created. This allows layout-dependent effects to be accounted for in pre-layout simulations, enabling designers to identify and correct performance issues early in the design process, thereby reducing the need for repeated post-layout simulation iterations and reducing overall design iteration time while maintaining simulation accuracy
2Reliability
If preset design rules are followed, then design reliability is improved, but design flexibility deteriorates
Solution Approach 1:
The patent applies dynamics by implementing a system where RC information is dynamically extracted and updated based on the actual layout geometry and interconnect structures. Rather than relying on static preset design rules, the system adaptively generates RC models that reflect the true electrical characteristics of the layout, allowing designers to maintain reliability while having the flexibility to explore different layout configurations and design options
3Measurement precision
If cross-probing between p-cell symbols and layouts is enabled, then design verification accuracy is improved, but system complexity increases
Solution Approach 1:
The patent applies the intermediary principle by introducing a mapping mechanism that connects p-cell symbols with their corresponding layout instances. This intermediary system enables accurate cross-probing and verification by tracking the relationship between schematic-level p-cells and their physical layout representations, improving design verification accuracy while managing system complexity through automated association and identification protocols
Data Source
AI summary
A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.