Integrated Circuit Design Pattern Correction for Lithography Accuracy
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Solution Overview
Problem
As IC technologies progress to smaller nodes, simply scaling down designs leads to inaccurate or poorly shaped device features, such as rounded corners, pinching, necking, bridging, and metal line thickness variations, affecting device performance, and existing optical proximity correction (OPC) methods are insufficient to address these issues effectively.
Innovation Solution
The implementation of enhanced IC manufacturing processes involving optical proximity correction (OPC), mask rule checking (MRC), and lithography process checking (LPC) to modify design patterns, insert assist features, and generate assistant data that includes factors like Mask Error Enhancement Factor (MEEF), Intensity Log Slope (ILS), and Depth of Focus (DOF) to improve feature accuracy and precision during mask and wafer fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design patterns are scaled down to smaller technology nodes, then production efficiency increases and costs decrease, but device feature accuracy and shape precision deteriorate
Solution Approach 1:
The patent applies optical proximity correction (OPC) to modify design patterns before fabrication. This preliminary action adjusts the patterns to anticipate and compensate for manufacturing distortions that will occur during lithography, thereby maintaining feature accuracy at smaller nodes while preserving the benefits of scaling for production efficiency
Solution Approach 2:
The patent inserts assist features into the design pattern to counteract the harmful effects of optical proximity. These assist features pre-compensate for diffraction and interference effects that would otherwise cause rounding, pinching, and bridging, thereby preventing accuracy deterioration while allowing continued scaling for improved productivity
2Manufacturing precision
If optical proximity correction (OPC) is applied to modify design patterns, then device feature accuracy improves, but manufacturing process complexity increases
Solution Approach 1:
The patent employs automated OPC algorithms that self-adjust design patterns based on simulated lithography outcomes. This self-service approach systematically handles the complexity of corrections without requiring manual intervention, thereby improving feature accuracy while managing process complexity through automation
Solution Approach 2:
The patent uses iterative OPC processes where simulated lithography results feed back into pattern modifications. This feedback loop continuously refines the design patterns to achieve target accuracy, managing the complexity through systematic automation rather than manual processes
3Measurement precision
If assist features are inserted and design patterns are modified, then lithography precision improves, but data processing and mask fabrication complexity increase
Solution Approach 1:
The patent performs OPC and inserts assist features during the data preparation phase before mask fabrication. This preliminary action consolidates data processing tasks upfront, improving lithography precision while managing complexity by completing modifications before the manufacturing workflow begins
Data Source
AI summary
Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, the design layout having a main feature; performing a process correction to the main feature thereby generating a modified main feature; using a computer, generating a simulated contour of the modified main feature, the simulated contour having a plurality of points; generating a plurality of assistant data in computer readable format, wherein each assistant data includes at least one process performance factor associated with one of the points; and keeping the simulated contour and the assistant data for use by a further process stage, such as mask making, mask inspection, mask repairing, wafer direct writing, wafer inspection, and wafer repairing.