Deep Reinforcement Learning for IC Design Rule Violation Patching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit design, existing methods for addressing design rule violations during detail routing are inefficient, as the order of violations to be patched is predefined, leading to additional violations being generated, which can result in repeated iterations and unresolved issues due to the heuristic method used.
Innovation Solution
The application of a deep reinforcement learning framework that utilizes a policy gradient model and a value gradient model to optimize the decision-making process for patching design rule violations, allowing for smart ordering and minimizing the number of unresolved violations by selecting the most effective actions based on reward maximization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a predefined heuristic method is used to sort violations, then the patching process is simple to implement, but additional violations are generated and the number of iterations increases
Solution Approach 1:
The patent changes the sorting parameters from simple heuristic rules to a multi-dimensional evaluation system that considers violation severity, spatial relationships, and potential impact on other violations. This allows the system to prioritize patches that will minimize additional violations while maintaining implementation feasibility through automated scoring.
Solution Approach 2:
The patent implements a feedback mechanism where the results of each patching iteration are analyzed to update the sorting criteria for the next iteration. The system learns from generated violations and adjusts the violation sorting order dynamically, reducing the number of iterations needed while keeping the implementation process manageable through automated feedback loops.
2Stability of the object's composition
If violations are patched one by one in sorted order, then the process is systematic, but repeated iterations are required and some violations remain unresolved
Solution Approach 1:
The patent performs preliminary analysis of all violations before patching begins, sorting them in an optimized order that anticipates potential generated violations. By pre-calculating the most effective patching sequence based on spatial relationships and violation characteristics, the system reduces the number of iterations needed while maintaining systematic processing throughout the patching operations.
Solution Approach 2:
The patent makes the violation sorting order dynamic rather than static, allowing the priority order to change based on the current state of the circuit after each patching iteration. The system dynamically re-evaluates and re-sorts violations based on updated spatial relationships and newly generated violations, reducing iterations while preserving systematic methodology.
3Reliability
If the violation list is sorted by design rules, then the patching follows a consistent order, but the number of remaining violations is high and correlated to the sorting order
Solution Approach 1:
The patent creates a composite sorting criterion that combines multiple factors including design rule violations, spatial relationships between violations, severity weights, and predicted impact on other violations. This composite approach maintains the consistency and reliability of a structured sorting process while significantly reducing the number of remaining violations by considering multiple dimensions rather than relying on a single design rule-based order.
Data Source
AI summary
A method of improving a design rule fixing process comprises receiving an integrated circuit design, including layout elements, and identifying a plurality of design rule violations in the integrated circuit design. The process then identifies a plurality of possible actions, each action comprising fixing a design rule. The process then uses a deep learning algorithm to select an action, the action representing fixing of a particular design rule violation. The process then comprises applying a first patch, based on the order returning to step (b) to select a next patch to apply.