IC Design Transformation for Formal Verification
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Solution Overview
Problem
Existing formal verification methods struggle to effectively verify the equivalence of retimed integrated circuit (IC) designs due to structural differences caused by retiming operations, which disrupt the scalability of combinational equivalency checking tools.
Innovation Solution
A method that encodes a reference IC design with logical relationships describing the movement of sequential cells across combinational logic, using white boxes and their functionally inverse black boxes to transform both designs, allowing for combinational equivalence checking without requiring structural similarity between the reference and implementation designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If retiming operations are performed to optimize IC design, then performance and area are improved, but structural differences are introduced that make formal verification difficult
Solution Approach 1:
Instead of trying to make the retimed design match the reference design structure, the patent inverts the approach by adding dummy sequential cells to the reference design to match the retimed structure. This allows the verification tool to work with structurally different designs by making the reference design adapt to the implementation design's structure rather than forcing the implementation to match the reference.
Solution Approach 2:
The patent introduces dummy sequential cells as intermediary elements that act as placeholders to maintain structural correspondence between the reference and retimed designs. These dummy cells serve as mediators that allow the formal verification tool to establish structural equivalence without requiring actual structural similarity, enabling verification of retimed designs with different architectures.
2Loss of time
If sequential cells are moved across combinational logic during retiming, then delay is optimized, but compare point matching becomes impossible
Solution Approach 1:
The patent creates copies of sequential cells in the form of dummy sequential cells that are inserted into the reference design at locations corresponding to the retimed sequential cells. These copies maintain the structural framework needed for compare point matching while allowing the actual sequential cells to be moved during retiming for delay optimization.
Solution Approach 2:
The patent changes the structural parameters of the reference design by adding dummy sequential cells, transforming it from a structurally identical design to one that accommodates structural differences. This parameter change enables the verification system to handle designs where sequential cells have been moved, merged, or duplicated during retiming.
3Area of stationary object
If sequential cells are merged or duplicated during retiming, then area is optimized, but equivalence verification becomes intractable
Solution Approach 1:
Instead of requiring the reference design to match the retimed design's merged or duplicated structure, the patent inverts the approach by adding corresponding dummy sequential cells to the reference design. This allows the reference design to adapt to the implementation's structure, making equivalence verification tractable even when sequential cells have been merged or duplicated for area optimization.
Data Source
AI summary
A memory is encoded with data that represents a reference IC design, a retimed IC design, and logical relationships, wherein at least one logical relationship describes combinational logic without reference to structural information, such as actual cells that have been instantiated in the IC designs. The logical relationships are used to instantiate logic described therein, and to define one or more black boxes as being functionally inverse of the logic. Each instantiated logic and its functionally inverse black box are thereafter added to the reference IC design to obtain a transformed reference IC design. A transformed retimed IC design is also obtained by addition of the instantiated logic(s) and functionally inverse black box(es) to the retimed IC design. These two transformed IC designs are then supplied to an equivalence checker, for formal verification.