Integrated Circuit Deskew via Multiphase Clock Shifting
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Solution Overview
Problem
As data bus speeds increase, signal skew between bits and the bus clock signal leads to errors in data transfer, limiting design flexibility and efficiency in integrated circuits, and existing methods to reduce skew often require multiple design iterations or restrict desirable IC and board layouts.
Innovation Solution
The implementation of data output circuits with adjustable multiphase clock signal generators and selectors that shift clock signals relative to a reference clock, allowing for dynamic deskew operations and improved signal alignment across data buses, using phase locked loops or delay locked loops to control clock signals applied to data output buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data bus speed is increased, then productivity is improved, but signal skew increases causing data transfer errors
Solution Approach 1:
The patent implements dynamic skew compensation by making the clock signal phases adjustable and reconfigurable. Each data output buffer can be individually timed by selecting from multiple clock phases, allowing the system to adapt to varying skew conditions dynamically rather than being fixed during design. This resolves the contradiction by enabling high-speed operation while maintaining reliability through adaptive timing adjustment.
Solution Approach 2:
The patent changes the timing parameter of clock signals by generating multiple phases with different time offsets. By varying the phase selection for each data output buffer, the system can compensate for skew effects without changing the fundamental data bus speed. This allows maintaining high productivity while improving reliability through parameter adjustment.
2Reliability
If skew is reduced by careful design of devices and wiring, then data transfer accuracy is improved, but design flexibility is reduced requiring multiple iterations
Solution Approach 1:
The patent performs preliminary skew measurement and compensation setup through the deskew control logic. By measuring actual skew conditions and pre-configuring the appropriate clock phase selections before normal operation, the system eliminates the need for multiple design iterations. The deskew control circuit automatically determines optimal timing parameters, resolving the contradiction between reliability and design complexity.
Solution Approach 2:
The system performs self-adjustment of clock phases through the deskew control logic that automatically measures and compensates for skew conditions. This self-service capability eliminates the need for external design iterations and manual adjustments, allowing the device to optimize its own timing parameters. This resolves the contradiction by making the system self-configuring rather than requiring complex external design processes.
3Reliability
If IC design is constrained to reduce skew, then data transfer accuracy is improved, but adaptability to different board layouts is reduced
Solution Approach 1:
The patent implements a universal deskew compensation mechanism that can adapt to any board layout through programmable clock phase selection. The multiphase clock generator and selector circuitry provide a universal solution that works regardless of specific wiring variations or board configurations. This resolves the contradiction by making the IC adaptable to different board layouts while maintaining data transfer accuracy through software-configurable timing adjustment.
Data Source
AI summary
A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal. The clock signal selector may include a plurality of clock signal selectors, respective ones of which receive the plurality of clock signals and selectively apply the plurality of clock signals to respective ones of the data output buffers responsive to the second control signal.