IC Failure Diagnosis via Tagged Scan Component Coordinates
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Solution Overview
Problem
The integration of intellectual property (IP) circuits from different vendors into semiconductor chips leads to challenges in diagnosing failures, as fabricators lack necessary information, resulting in delayed throughput and confidentiality issues when sending entire chips back to IP vendors for diagnosis.
Innovation Solution
A process where IP vendors label scan components with tagging texts following a predetermined sequence, which are included in a physical description file, allowing chip fabricators to extract and sort coordinates to generate a format file for diagnosing failures within the chip without sending the entire chip back to the IP vendor, enabling on-site diagnosis and maintaining confidentiality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the whole chip is sent back to the IP vendor for diagnosis, then the IP vendor can determine the cause of failure, but the throughput of the fabricator is severely affected and confidentiality issues arise
Solution Approach 1:
The patent segments the diagnosis process by extracting and analyzing only the specific failed IP circuit portion from the entire chip, rather than sending the whole chip to the vendor. This allows the fabricator to perform localized diagnosis on the defective segment while keeping the rest of the production flow moving, thus maintaining throughput while achieving accurate failure analysis.
Solution Approach 2:
The patent introduces an intermediary approach where the fabricator performs preliminary diagnosis using extracted IP circuit information before involving the IP vendor. This intermediary step filters out cases that can be resolved locally, reducing the number of chips that need to be sent to vendors and thereby maintaining fabricator productivity.
2Reliability
If the whole chip is sent back to the IP vendor for diagnosis, then the cause of failure can be determined, but confidentiality issues arise as other IP circuits are exposed
Solution Approach 1:
The patent extracts only the specific failed IP circuit portion from the entire chip for analysis, separating it from other confidential IP circuits. This extraction allows the fabricator to diagnose the failure cause while keeping other proprietary IP circuits confidential and retained on the fabricator's side.
Solution Approach 2:
The patent segments the chip information into the specific failed IP circuit portion and other confidential portions. Only the necessary failed segment is analyzed or shared, while other IP circuits remain confidential on the fabricator's side, thus preventing information loss while maintaining diagnosis accuracy.
3Reliability
If the fabricator does not have enough information to diagnose the failed IP circuit, then the diagnosis must be sent back to the IP vendor, but this extends the time to determine the cause of failure
Solution Approach 1:
The patent performs preliminary action by extracting and preparing the failed IP circuit information locally at the fabricator before involving the IP vendor. This preliminary extraction and analysis setup enables faster diagnosis by having the necessary information ready in advance, reducing the overall time to determine the failure cause.
Solution Approach 2:
The patent enables the fabricator to perform self-service diagnosis by providing tools and methods to extract and analyze IP circuit information locally. This self-service capability allows the fabricator to handle diagnoses independently when possible, reducing dependency on external vendors and minimizing time loss.
Data Source
AI summary
A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.