Diagonal Power Patch Layout for IC Power Integrity
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Solution Overview
Problem
As integration levels in integrated circuits increase, the limited degree of freedom in arranging power delivery network lines results in inefficient power distribution, leading to voltage drops and reduced power integrity.
Innovation Solution
Incorporating diagonal power patterns with overlapping rectangular patches across multiple wiring layers, interconnected by vias, to create a robust and efficient power delivery network that aligns with standard cell arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a grid power delivery network is used, then power can be supplied evenly throughout the integrated circuit, but the degree of freedom in arranging power lines is limited due to increased integration level and signal wires
Solution Approach 1:
The patent transitions from a traditional two-dimensional grid power delivery network to a three-dimensional stacked power delivery network. Power lines are arranged in multiple wiring layers (first wiring layer, second wiring layer, third wiring layer) stacked vertically, with via holes connecting corresponding power lines across layers. This vertical stacking provides additional spatial dimensions for power line arrangement, significantly increasing the degree of freedom in routing while maintaining effective power distribution across the integrated circuit.
2Productivity
If more wires for transmitting signals are formed in wiring layers, then integration level increases, but the degree of freedom in arranging power delivery network lines is reduced
Solution Approach 1:
The patent utilizes vertical stacking of multiple wiring layers to provide additional routing dimensions for power lines. Instead of being constrained to a single planar layer where signal wires occupy available space, the power delivery network extends into the vertical dimension with multiple stacked layers connected by via holes. This allows power lines to be routed in three-dimensional space, maintaining arrangement flexibility even as integration level increases and signal wire density increases in each individual layer.
3Device complexity
If power lines are arranged in a limited manner due to integration constraints, then layout complexity is reduced, but voltage drops increase and power integrity deteriorates
Solution Approach 1:
The patent implements a stacked power delivery network with multiple wiring layers arranged vertically and connected through via holes. This three-dimensional arrangement allows power lines to be positioned closer to standard cells in the vertical dimension, reducing current path lengths and minimizing voltage drops. The multi-layer structure provides redundant power delivery paths and improves power integrity without requiring excessive layout complexity in any single plane.
Solution Approach 2:
The patent embeds multiple power delivery networks within each other across different wiring layers. The first, second, and third wiring layers form nested structures where each layer contains power lines that complement and support the others. Via holes act as connectors that nest the vertical stack into a unified three-dimensional power delivery system, allowing efficient power distribution while managing layout complexity through hierarchical organization.
Data Source
AI summary
An integrated circuit includes a standard cell, a power rail extending in a first direction in a first wiring layer and configured to supply power to the standard cell, and an upper power pattern disposed in a second wiring layer above the first wiring layer. The upper power pattern includes a plurality of rectangular upper power patches extending in the first direction, and configured to supply power to the power rail. Corner portions of the plurality of upper power patches overlap each other in a direction between the first direction and a second direction that intersects the first direction.