IC Interconnect Diamond Heat Dissipation Under BEOL Thermal Limits

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Solution Overview

Problem

The challenge in semiconductor integrated circuit (IC) manufacturing is the difficulty in integrating high-temperature processes, such as growing diamond layers, within the thermal budget constraints of back-end-of-line (BEOL) processes, which are typically limited to lower temperatures.

Innovation Solution

The method involves growing diamond layers on a separate carrier substrate at high temperatures and then transferring them onto the signal transmission structure, allowing integration into the IC while adhering to BEOL thermal budgets by using a composite dielectric layer with adhesive layers, enabling efficient heat dissipation and signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If diamond layers are grown at high temperatures to improve heat dissipation performance, then thermal conductivity is improved, but the BEOL thermal budget constraint is violated

Engineering Contradiction:
Improvediamond layer growth temperatureVSAvoidBEOL process compatibility
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The manufacturing process is divided into two independent segments: (1) growing diamond layers at high temperatures on a separate carrier substrate, and (2) transferring the pre-grown diamond layers to the BEOL structure at low temperatures. This segmentation allows the diamond layer formation to occur under optimal high-temperature conditions while the BEOL process maintains its low-temperature constraints, resolving the contradiction between thermal conductivity requirements and process compatibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The diamond layers are preliminarily grown on the carrier substrate before being transferred to the final BEOL structure. By performing the high-temperature diamond growth action in advance on a separate substrate, the patent enables the diamond layers to be formed under optimal conditions without exposing the temperature-sensitive BEOL components to high temperatures, thus maintaining both high thermal conductivity and BEOL process compatibility.

Inventive Principle:
Principle #10Preliminary action

2Temperature

If diamond layers are integrated directly into BEOL structures, then heat dissipation is improved, but manufacturing complexity increases due to process integration difficulties

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The carrier substrate serves as an intermediary that facilitates the integration of diamond layers into BEOL structures. The diamond layers are grown on this intermediate carrier substrate under high temperatures, then transferred to the final BEOL structure. This intermediary approach simplifies the overall manufacturing process by decoupling the diamond growth step from the BEOL integration step, reducing process complexity while maintaining heat dissipation effectiveness.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the integration of high-temperature diamond layers into ICs without exceeding BEOL thermal limits, enhancing performance and lifetime by effective heat dissipation and maintaining electrical connectivity.

Implementation Method 1

the first heat dissipation layer may be in direct contact with the interconnect structure to reduce the likelihood of overheating and potential damage

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The composite dielectric layer may include an adhesive layer and the first heat dissipation layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS20250210446A1Integrated circuit and manufacturing method thereof
Publication Date: 2025.06.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250210446A1 patent drawing
  • US20250210446A1 patent drawing
  • US20250210446A1 patent drawing

AI summary

An integrated circuit includes a semiconductor substrate and an interconnect structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes a signal transmission structure and a heat dissipation structure. The heat dissipation structure is disposed on the signal transmission structure and includes a composite dielectric layer and first conductive features. The composite dielectric layer includes an adhesive layer and a diamond layer disposed on the adhesive layer. The first conductive features are embedded in the composite dielectric layer.