IC Dice Edge Finishing via Trench Etching
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Solution Overview
Problem
The existing methods for fabricating semiconductor integrated circuits face challenges in achieving reliable edge finishing and minimizing contaminant diffusion, particularly in small-sized ICs directly assembled on boards, which affects cost and reliability due to exposed interfaces and inefficient use of wafer area.
Innovation Solution
The method involves forming trenches around the ICs on the wafer substrate to define their perimeter, filling these trenches with a protective material, and back-lapping the wafer to separate the ICs, resulting in a uniform protective layer that reduces contaminant diffusion and minimizes wasted wafer area through precise photolithographic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a top passivation layer is formed on the IC chip to limit contaminant occurrence, then reliability is improved, but the finishing at the chip's edge sidewalls remains a potential source of contaminants
Solution Approach 1:
The patent extracts and removes the problematic edge regions containing contaminants through selective etching processes. The method identifies and removes damaged or contaminated sidewall regions at the chip edges, eliminating the source of contaminant diffusion while preserving the protected regions covered by passivation layers.
Solution Approach 2:
The patent applies preliminary protective measures by forming passivation layers on the chip surface before contamination can occur, and then performs selective removal of edge regions that would otherwise be exposed to contaminants. This preemptive approach prevents contaminant diffusion while maintaining the integrity of the protected areas.
2Adaptability or versatility
If the chip size is reduced to meet space and weight constraints, then adaptability is improved, but the edge finishing problem becomes more severe
Solution Approach 1:
The patent applies different treatments to different regions of the chip: protected regions receive passivation layer coverage while edge regions undergo selective removal or special finishing. This localized approach allows small chip sizes to maintain reliability by treating each region according to its specific contamination risk.
3Manufacturing precision
If inter-dice separation scribe lanes are used to separate ICs on the wafer, then manufacturing precision is improved, but wafer area is wasted
Solution Approach 1:
The patent replaces the traditional mechanical scribe lane separation method with a chemical etching process that uses defined separation trenches. This substitution eliminates the need for wide mechanical cutting paths while maintaining precise separation, thereby reducing wasted wafer area.
Solution Approach 2:
The patent changes the separation method from mechanical cutting with fixed width scribe lanes to chemical etching with controllable trench dimensions. By adjusting etching parameters such as depth, width, and positioning, precise separation is achieved with minimal wafer area consumption.
Data Source
AI summary
In various embodiments, an integrated circuit die is provided. The integrated circuit die may include a circuit on a surface of a semiconductor substrate that has a peripheral sidewall extending substantially perpendicular to and away from the surface. A first protective layer may cover the sidewall of the semiconductor substrate and peripheral edges of the circuit to provide protection from contaminant diffusion. In some embodiments, a semiconductor substrate is provided that has a plurality of dice contained thereon. Each of the dice may have an integrated circuit region and a peripheral sidewall etched into the semiconductor substrate. A first protective layer may be used to cover the peripheral sidewall of the semiconductor substrate to provide protection from contaminant diffusion. Additional apparatuses, systems, and methods are disclosed.