IC Die Repackaging With Backside Trench for Fault Signal Detection
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Solution Overview
Problem
As IC chips progress to more advanced technology nodes, the debugging process becomes increasingly difficult due to metallization components on both sides of the substrate, which block or obstruct signals emitted by the IC chip during testing.
Innovation Solution
A novel packaging and testing process flow is introduced to repackaging an IC chip by forming an opening or trench on the back side that extends at least partially through the metallization components, allowing signals to be detected without obstruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IC chips are manufactured with metallization components on both sides to enable advanced functionality, then device functionality is improved, but signal detection during debugging is blocked
Solution Approach 1:
The patent divides the substrate into multiple segments by creating openings that expose specific regions. This segmentation allows different areas of the chip to be accessed independently for debugging purposes, enabling signal detection through the openings while maintaining the complete metallization structures on both sides for device functionality.
Solution Approach 2:
The patent introduces an intermediary debugging structure that includes openings in the substrate and associated debugging circuitry. This intermediary structure mediates between the dual-sided metallization components and the debugging equipment, allowing signals to be detected through the openings without disrupting the functional metallization layers.
2Ease of operation
If existing debugging processes are used on IC chips with dual-sided metallization, then debugging can be performed, but signal detection is obstructed by metallization components
Solution Approach 1:
The patent implements preliminary action by pre-configuring the substrate with openings and debugging structures before the debugging process begins. The openings are formed and debugging circuitry is integrated in advance, so that when debugging is performed, signal detection can proceed without obstruction from metallization components.
3Productivity
If scaling down continues to increase production efficiency, then manufacturing cost is reduced, but fabrication challenges increase
Solution Approach 1:
The patent addresses fabrication challenges by transitioning to another dimension - creating openings that extend through the substrate thickness dimension. This vertical/dimensional approach to accessing signal paths allows debugging capability to be added without increasing lateral complexity or affecting the scaled-down circuit dimensions that drive production efficiency.
Data Source
AI summary
A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.