Laterally Mounted IC Die Package with Dissimilar Copper Pillars
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Solution Overview
Problem
Conventional chip packages with dissimilar solder joint heights are prone to cracking and redistribution layer damage due to significant grinding required to accommodate tolerance stacks, leading to thermo-mechanical reliability issues in integrated circuit interconnects.
Innovation Solution
The method involves replacing original solder interconnects with copper pillars of different compositions, forming a redistribution layer on these pillars, and creating solder connections to a substrate, which reduces material removal and stress on the redistribution layer, enhancing the reliability of the solder joints between IC dies and the package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If significant pillar grinding is performed to accommodate tolerance stacks in packages with dissimilar solder joint heights, then the solder joints can be made coplanar, but cracking is initiated in the redistribution layer causing damage to the routings
Solution Approach 1:
The patent applies preliminary action by pre-forming copper pillars of different heights at different locations before mounting the IC dies. This allows the solder joints to be made coplanar through controlled copper removal after die attachment, rather than requiring extensive grinding that would crack the redistribution layer. The preliminary height differentiation accommodates tolerance stacks while preserving redistribution layer integrity.
Solution Approach 2:
The patent implements local quality by creating spatially varying copper pillar heights at different locations on the substrate. This local differentiation allows each pillar to be optimized for its specific position, accommodating dissimilar solder joint heights from different IC dies while maintaining overall coplanarity after controlled removal, thus preventing redistribution layer cracking.
2Adaptability or versatility
If dissimilar solder joint heights are used to accommodate different IC dies, then more die configurations can be integrated, but the redistribution layer becomes prone to cracking and failure
Solution Approach 1:
The patent uses preliminary action by pre-establishing a network of copper pillars with differentiated heights before IC die attachment. This preliminary structure provides a flexible foundation that can accommodate various die configurations with dissimilar solder joint heights, while the controlled subsequent removal process ensures coplanarity is achieved without cracking the redistribution layer, thus maintaining reliability.
Solution Approach 2:
The patent introduces copper pillars as an intermediary element between the substrate and IC dies. These pillars act as a mediator that absorbs height variations from dissimilar solder joints, allowing flexible die configurations while protecting the redistribution layer from stress-induced cracking through controlled selective removal.
3Manufacturing precision
If extensive grinding is performed to make solder joints coplanar, then tolerance stacks are accommodated, but crack initiations occur that propagate into the redistribution layer
Solution Approach 1:
The patent applies preliminary action by pre-forming copper pillars with differentiated heights that are optimized for their specific locations. This preliminary configuration accommodates tolerance stacks from dissimilar solder joints, and the controlled subsequent removal process achieves coplanarity with minimal material removal, preventing crack initiation and propagation into the redistribution layer.
Solution Approach 2:
The patent implements parameter changes by selectively removing copper material from pillars of different initial heights. This controlled parameter modification (height reduction) achieves coplanarity while minimizing the total amount of material removal, thereby preventing the mechanical stress that would initiate and propagate cracks in the redistribution layer.
Data Source
AI summary
A chip package assembly and method of fabricating the same are described herein. The chip package assembly generally includes at least one integrated circuit (IC) die that has had the original solder interconnects at least partially replaced to enhance the reliability of a redistribution layer disposed between the IC die and the substrate. In the resulting chip package assembly, at least one IC die includes first and second pillars extending from exposed contact pads through a first mold compound. The second pillars are fabricated from a material that has a composition different than that of the first pillars. A redistribution layer is formed on the first and second pillars. The solder interconnects mechanically couple the redistribution layer to landing pads of a substrate. The solder interconnects also electrically couple circuitry of the substrate to the circuitry of the IC die through the redistribution layer and first and second pillars.