IC Die Heat Dissipation Layer for Thermal Management

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Solution Overview

Problem

Current heat dissipation methods for IC chips are limited in reducing temperatures at high-power density regions due to the physical limitations of heat sinks being unable to be infinitely close to the IC die, resulting in inadequate cooling and restricted chip performance.

Innovation Solution

An integrated circuit die with a heat dissipation layer made of an electrical-insulating material with higher than a preset heat conductivity, covering regions above the interconnection layer except for the metal welding pad, and located under a plastic packaging layer, allowing for enhanced heat spreading and increased dissipation area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a heat sink is added to an IC chip package structure, then heat dissipation capability is improved, but the heat sink cannot be infinitely close to the IC die due to physical limitations of package technology and structure

Engineering Contradiction:
Improveheat point temperatureVSAvoiddistance from heat sink to IC die
Core Design Contradiction:
TemperatureVSLength of moving object

Solution Approach 1:

The patent transitions from a traditional heat sink positioned at the package level to a heat dissipation layer integrated within the IC die structure itself. This dimensional repositioning allows the heat dissipation functionality to be embedded at the source of heat generation, eliminating the distance limitation imposed by external package structures while maintaining effective heat management.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The heat dissipation layer is nested within the interconnection layer structure of the IC die, specifically positioned between metal layers. This nesting approach integrates the heat dissipation function directly into the existing die architecture, allowing the heat dissipation structure to occupy space within the die thickness rather than requiring additional external volume.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If a heat sink is added to an IC chip package, then heat dissipation area is increased, but the heat sink is mostly located on the plastic packaging material rather than close to the IC die

Engineering Contradiction:
Improveheat dissipation areaVSAvoidchip working reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent redistributes the heat dissipation area from the horizontal plane at the package level to the vertical dimension within the IC die structure. By positioning the heat dissipation layer between metal layers inside the die, the solution creates heat dissipation pathways closer to heat sources while maintaining adequate dissipation area through the die thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The heat dissipation layer is selectively positioned in regions where heat generation is most intense, specifically between metal layers that carry high current or are adjacent to active components. This localized approach concentrates heat dissipation capacity where it is most needed, improving reliability without requiring uniform heat dissipation across the entire package area.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively increases the heat dissipation area and capability of the IC chip by allowing the heat dissipation layer to be closer to the IC die, rapidly spreading heat from high-power density regions to the chip surface, thereby improving temperature management and chip performance.

Implementation Method 1

the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value... rapidly spreading heat from high-power density regions to the chip surface

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Data Source

PatentUS10607913B2Integrated circuit die and manufacture method thereof
Publication Date: 2020.03.31 HUAWEI TECH CO LTD
  • US10607913B2 patent drawing
  • US10607913B2 patent drawing
  • US10607913B2 patent drawing

AI summary

The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.