IC Die Defect Mapping With Keep-Out Zones for SKU Salvage
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Solution Overview
Problem
In the production of programmable integrated circuits, high defect rates in silicon dies lead to low yield and render many dies unusable, as existing methods relying on redundant circuitry are costly and inefficient, especially in leading-edge process technology nodes.
Innovation Solution
Generating defect maps for integrated circuit dies and using integrated circuit design tools to create 'keep-out zones' that block off defective regions, allowing for the creation of Stock Keeping Units (SKUs) with reduced logic density and performance, which can be sold to customers who do not require full functionality, thereby increasing the number of sellable dies per wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant circuitry is used to repair defective logic regions, then the reliability of the integrated circuit is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes defective logic regions from the circuit by identifying them through testing and excluding them from further design and operation. This is achieved by creating defect maps that pinpoint problematic areas, allowing the rest of the circuit to function normally without requiring complex redundant circuitry to compensate for every defect.
Solution Approach 2:
Instead of applying full redundancy across the entire circuit, the patent applies partial action by selectively blocking only the specific defective regions identified through testing. This partial blocking approach provides sufficient reliability for the functional portions while avoiding the overhead of comprehensive redundancy schemes.
2Productivity
If redundant circuitry is implemented for defect resiliency, then the yield of functional dies is improved, but the manufacturing cost increases due to die-bridging technologies
Solution Approach 1:
The patent extracts defective regions through systematic testing and defect mapping, removing them from the functional circuit area. This extraction approach increases yield by salvaging portions of dies that would otherwise be discarded, without incurring the high costs of die-bridging technologies required by traditional redundancy methods.
Solution Approach 2:
The patent changes the parameter of defect handling from active repair (requiring die-bridging) to passive exclusion through keep-out zones. This parameter change in the manufacturing approach significantly reduces costs while maintaining improved yield through the utilization of partially functional dies.
3Reliability
If full functionality is required for each die, then the reliability is maintained, but the number of sellable dies per wafer decreases due to high defect rates
Solution Approach 1:
The patent applies local quality by creating spatially varying functionality across the wafer. Different regions of different dies have different functional capabilities based on their defect profiles, with keep-out zones tailored to each die's specific defects. This allows maximization of yield by selling dies with appropriate functionality levels to matching applications.
Solution Approach 2:
The patent segments the wafer into individual die units with unique defect maps and keep-out zone configurations. This segmentation allows each die to be independently evaluated and marketed based on its specific functional capabilities, transforming a uniform high-reliability requirement into differentiated product tiers that increase overall yield.
4Reliability
If defective dies are scrapped to maintain quality standards, then the product reliability is ensured, but the loss of substance increases
Solution Approach 1:
The patent converts the harm of silicon defects into a benefit by using defect maps to create customized keep-out zones that enable the sale of previously unusable dies. Defective dies are transformed into lower-tier SKUs with reduced functionality, turning waste material into revenue-generating products and significantly reducing loss of usable die material.
Data Source
AI summary
A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.