IC Die Structure for Leakage Isolation After Wafer Separation

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Solution Overview

Problem

IC dies experience leakage currents due to physical damage during separation, necessitating mechanisms to prevent such leakage.

Innovation Solution

An integrated circuit die forming method that includes forming devices in separate areas with a metal layer connection and a scribe area, utilizing synchronization components for Class-D amplifiers and devices to prevent leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If IC dies are separated into single dies, then adaptability and ease of use are improved, but leakage currents occur due to physical damage

Engineering Contradiction:

ImproveadaptabilityVSAvoidleakage current

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent forms isolation structures and protective mechanisms during the wafer fabrication process before the dies are separated. This preliminary action ensures that when dies are eventually separated into single units, the isolation structures are already in place to prevent leakage currents caused by physical damage during separation and subsequent use.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces isolation structures as intermediary elements between adjacent dies on the wafer. These isolation structures act as mediators that electrically isolate the dies from each other and protect against leakage currents that would occur during separation, allowing the dies to function reliably as individual units.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If isolation structures are formed between dies, then leakage current prevention is improved, but device complexity increases

Engineering Contradiction:

Improveleakage current preventionVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of isolation structures with the existing wafer fabrication process steps. By merging the isolation structure formation into the standard manufacturing flow, the patent achieves leakage current prevention without significantly increasing overall device complexity or requiring separate specialized processing steps.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The isolation structures serve multiple functions simultaneously: they electrically isolate adjacent dies, prevent leakage currents during separation, and provide mechanical support. This multi-functionality reduces the need for additional specialized structures, thereby limiting the increase in device complexity while achieving comprehensive leakage prevention.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12463135B2IC die forming method and IC die structure

Publication Date: 2025.11.04 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC

AI summary

An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.