IC Die Sidewall Ledges for Delamination-Resistant Packaging
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Solution Overview
Problem
Current semiconductor device packaging technologies face reliability issues due to coefficient of thermal expansion (CTE) mismatch stress between the encapsulant and top IC dies, leading to interfacial delamination during thermal cycling processes.
Innovation Solution
The semiconductor wafer is singulated using multiple recessing processes to create top IC dies with uneven sidewalls, allowing the encapsulant to extend along these sidewalls and act as a jig, reducing delamination and enhancing bonding reliability between the top and bottom IC dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional singulation processes are used to create IC dies with flat sidewalls, then the manufacturing process is simple, but the encapsulant cannot effectively prevent interfacial delamination during thermal cycling
Solution Approach 1:
The patent applies asymmetry by creating uneven sidewalls on IC dies through multiple recessing processes with different widths. The first recess has a first width, the second recess has a second width narrower than the first, and the third recess has a third width narrower than the second, creating a stepped asymmetric profile that allows the encapsulant to act as a bonding jig and prevent delamination during thermal cycling.
Solution Approach 2:
The singulation process is segmented into multiple distinct recessing operations rather than a single cut. The first recessing process creates a first recess, the second recessing process creates a second recess with different dimensions, and the third recessing process creates a third recess, dividing the singulation into staged segments that create the uneven sidewall structure.
2Reliability
If multiple recessing processes are used to create uneven sidewalls, then interfacial delamination is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The uneven sidewalls are created through preliminary recessing actions before the final singulation step. The first, second, and third recessing processes prepare the die structure in advance, creating the asymmetric profile that will later serve as a bonding jig for the encapsulant, preventing delamination during subsequent thermal cycling.
Solution Approach 2:
The recessing processes create localized variations in the die structure by removing material to different depths and widths at different locations. The first recess has a first width, the second recess has a second width, and the third recess has a third width, creating local quality differences that form the uneven sidewall profile essential for delamination prevention.
3Ease of manufacture
If IC dies are singulated without creating uneven sidewalls, then the manufacturing process is straightforward, but the encapsulant cannot act as an effective bonding jig
Solution Approach 1:
The patent transforms the symmetric flat sidewall structure into an asymmetric uneven sidewall structure through multiple recessing processes. This asymmetry enables the encapsulant to mechanically interlock with the die structure, allowing it to function as a bonding jig that prevents interfacial delamination during thermal cycling while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor device and a forming method thereof are provided. The semiconductor device includes an integrated circuit (IC) die and an encapsulant. The IC die includes a semiconductor substrate and an interconnect structure connected to the semiconductor substrate, the semiconductor substrate includes a first ledge, and the interconnect structure includes a second ledge. The encapsulant extends along the first ledge of the first semiconductor substrate and the second ledge of the first interconnect structure.