IC Disposition Using Ring Oscillator Frequency Screening
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Solution Overview
Problem
Integrated circuit (IC) manufacturing faces challenges due to timing misalignments caused by manufacturing process variations, leading to unpredictable results and defective ICs, which are often discarded without proper initial screening.
Innovation Solution
A method for IC disposition that uses performance-sensitive ring oscillators (PSROs) to determine disposition criteria based on statistical timing measurements, allowing for earlier identification and rejection of defective ICs, thereby increasing yield and quality by aligning acceptance regions with operational regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ICs are tested using traditional at-speed structure test (ASST) and functional testing, then testing accuracy is improved, but testing time is increased and yield is reduced due to late identification of defective ICs
Solution Approach 1:
The patent applies preliminary action by performing initial screening of ICs using ring oscillator frequency measurements before conducting full ASST and functional testing. This early disposition step identifies and discards obviously defective ICs based on frequency criteria, preventing waste of time on ICs that would fail anyway, while allowing potentially good ICs to proceed to more thorough testing.
2Productivity
If ICs are discarded based on negative slack without proper screening, then productivity is improved by quick rejection, but yield is reduced due to discarding potentially functional ICs
Solution Approach 1:
The patent changes the parameter used for initial screening from static slack values to dynamic ring oscillator frequency measurements. By measuring the actual operating frequency of ring oscillators and comparing against criteria derived from statistical timing analysis, the method identifies ICs that are truly defective versus those that merely have conservative slack margins, thereby maintaining high rejection efficiency while preserving yield of potentially functional ICs.
3Ease of operation
If design-independent acceptance regions are used for IC disposition, then ease of operation is improved, but manufacturing precision is reduced due to mismatch with operational regions
Solution Approach 1:
The patent applies feedback by using statistical timing analysis of the specific IC design to derive disposition criteria that are tailored to that design's characteristics. The ring oscillator frequency measurements are interpreted in the context of the design's timing requirements and process variations, creating acceptance regions that accurately reflect actual operational boundaries rather than using generic design-independent thresholds.
Data Source
AI summary
A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.