Integrated Circuit Dummy Gate Height for Memory-Core Integration
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Solution Overview
Problem
The integration of flash memory with peripheral/core circuitry on a single chip increases process complexity and difficulty due to differing device configurations in memory cells and peripheral/core circuitry, making it challenging to simplify the integration process.
Innovation Solution
A method for manufacturing an integrated circuit structure involves forming semiconductor word lines and memory cells with a height difference, using a dummy gate that is taller than the semiconductor word lines and gate, allowing for protection during removal without additional photomasks, and replacing the dummy gate with a metal gate, thus maintaining process simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory is integrated with peripheral/core circuitry on a single chip, then memory functionality is achieved, but process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies local quality by forming a dummy gate structure specifically in the core region that has different properties (height, material composition) than the semiconductor word lines in the memory region. This allows the dummy gate to be selectively removed while protecting the semiconductor word lines, thereby simplifying the integration process despite the heterogeneity of devices on the chip.
Solution Approach 2:
The dummy gate acts as an intermediary structure that facilitates the integration process. It is formed as a temporary structure during manufacturing that enables selective removal in the core region while protecting memory region structures. After serving its protective function, the dummy gate is removed and replaced with a metal gate, thus simplifying the overall integration process.
2Adaptability or versatility
If different device configurations are used in memory cells and peripheral/core circuitry, then device functionality is achieved, but integration difficulty increases
Solution Approach 1:
The patent implements local quality by creating region-specific structures: semiconductor word lines in the memory region and a dummy gate in the core region. The dummy gate has distinct properties (polysilicon material, greater height) that enable selective processing. This local differentiation allows the manufacturing process to accommodate different device configurations in different regions while maintaining overall process simplicity.
Solution Approach 2:
The dummy gate is formed in advance as a preliminary structure during the manufacturing process. This preliminary action enables subsequent selective removal in the core region while protecting memory region structures. The dummy gate serves as a temporary placeholder that simplifies the manufacturing sequence by allowing core region transistors to be formed before final metal gate integration.
3Manufacturing precision
If semiconductor word lines are protected during dummy gate removal, then manufacturing precision is improved, but additional process steps are required
Solution Approach 1:
The dummy gate structure provides self-service protection for the semiconductor word lines during its own removal process. The dummy gate's greater height creates a physical barrier that protects the shorter semiconductor word lines when etching or removing the dummy gate in the core region. This self-protecting mechanism eliminates the need for additional protective layers or complex masking processes.
Solution Approach 2:
The patent solves the protection problem by transitioning to another dimension - using height difference rather than lateral protection. The dummy gate is formed with greater height than the semiconductor word lines, creating a vertical dimension protection scheme. This dimensional approach allows selective removal through vertical etching while the taller dummy gate physically shields the shorter word lines, avoiding the need for additional horizontal protection layers.
Data Source
AI summary
A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.