Integrated Circuit Dummy Pattern Spacing for Lithography Integrity
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Solution Overview
Problem
Current methods for forming fine patterns in integrated circuits, such as double patterning and self-aligned double patterning, face challenges in maintaining pattern integrity and performance due to issues like pattern bridging and spacer thickness control, leading to reduced circuit performance.
Innovation Solution
The proposed solution involves designing an integrated circuit with specific signal and dummy patterns spaced by a predetermined width, where the dummy patterns are used to maintain pattern shape and integrity, and their placement is determined based on the pitch between mandrel and non-mandrel patterns, ensuring predictable shape formation and reduced width variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If double patterning or self-aligned double patterning is used to form fine patterns, then the pitch of patterns is reduced, but pattern bridging occurs and pattern integrity deteriorates
Solution Approach 1:
The patent applies preliminary action by forming spacer patterns before the final signal patterns. The spacers are deposited and etched to create mandrel patterns that guide subsequent lithography steps, ensuring that the final patterns are formed with correct dimensions and spacing before the actual signal routing is completed.
Solution Approach 2:
The patent uses spacer patterns as intermediary elements between the lithography process and the final signal patterns. These spacers act as mandrels that mediate the formation of the final conductive patterns, ensuring precise pitch control and preventing pattern bridging by serving as temporary structural guides.
2Shape
If self-aligned double patterning with spacers is used, then pattern separation is achieved, but spacer thickness control becomes difficult and pattern shape varies
Solution Approach 1:
The patent applies parameter changes by systematically varying the pitch between adjacent signal patterns and adjusting the corresponding spacer widths to maintain consistent spacing. By changing these geometric parameters in a controlled manner, the patent achieves uniform pattern shapes while maintaining proper separation, compensating for variations in spacer thickness through layout design rather than relying solely on process control.
3Productivity
If fine patterns are formed with reduced pitch, then degree of integration is enhanced, but circuit performance deteriorates due to pattern deformation
Solution Approach 1:
The patent applies local quality by designing different pitch values for different regions of the circuit layout. Critical signal paths maintain larger spacing to ensure signal integrity and prevent deformation, while non-critical areas use reduced pitch to maximize integration density. This localized differentiation allows the circuit to achieve high integration while maintaining performance in critical regions.
Data Source
AI summary
An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.