IC Edge Optimization for Deep Submicron Manufacturability

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Solution Overview

Problem

Conventional electronic design tools fail to effectively optimize edge characteristics in deep submicron designs, leading to manufacturability issues, reliability problems, and increased complexity in photomask production, especially at dimensions smaller than 65 nanometers.

Innovation Solution

A method and system for edge optimization in electronic design that reduces the number and length of edges in IC layouts during placement, routing, or as a post-optimization step, using techniques such as edge lengthening, removing small edges, and adjusting object widths to enhance manufacturability and yield, while ensuring compliance with design rules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional electronic design tools are used for deep submicron designs, then design complexity is reduced, but manufacturability and reliability deteriorate due to unoptimized edge characteristics

Engineering Contradiction:

ImprovemanufacturabilityVSAvoidedge characteristics complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent changes geometric parameters of layout objects by optimizing edge characteristics including edge length, edge count, and object width. The system automatically adjusts these parameters to meet minimum edge length requirements and reduce edge complexity, thereby improving manufacturability for deep submicron technologies without increasing design complexity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent performs edge optimization as a preliminary action before photomask fabrication and lithography processes. By optimizing edge characteristics in advance during the design phase, the system prevents manufacturability issues from arising, rather than addressing them during manufacturing or post-processing

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If the number of edges and edge length variations are reduced, then photomask production complexity and manufacturing defects are reduced, but design flexibility and routing options are constrained

Engineering Contradiction:

Improvephotomask production simplicityVSAvoidrouting flexibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic optimization process that adapts edge characteristics based on specific design contexts. The system evaluates multiple routing options and selectively applies edge optimization only where beneficial, maintaining routing flexibility in critical paths while simplifying edges in less critical areas, thus balancing manufacturability with design adaptability

Inventive Principle:

Principle #15Dynamics

3Ease of manufacture

If edge optimization is performed during placement and routing, then manufacturability is improved, but design cycle time and computational resources are increased

Engineering Contradiction:

ImprovemanufacturabilityVSAvoiddesign cycle time

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

The patent applies partial optimization by focusing computational efforts on critical edges and layout regions that have the greatest impact on manufacturability. The system identifies and optimizes only the most problematic edge characteristics rather than uniformly processing all edges, thereby improving manufacturability while minimizing additional design cycle time and computational overhead

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS7721235B1Method and system for implementing edge optimization on an integrated circuit design

Publication Date: 2010.05.18 CADENCE DESIGN SYST INC

AI summary

Disclosed is a method, system, and computer program product for performing edge optimization on an electronic design. According to some approaches, the number of edges and/or the length of edges within an IC design are configured for optimized manufacturability and yield of an integrated circuit. The edge optimization may occur in real-time during layout, placement, and/or routing, or occur in a post-optimization step.