Hierarchical IC Architecture with Elastomeric Connector

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Solution Overview

Problem

Current integrated circuit architectures face challenges in efficiently processing large volumes of data required for advanced artificial intelligence and machine learning applications, leading to economic inefficiencies and inadequate data processing capabilities due to limitations in existing computer architectures.

Innovation Solution

The development of an advanced integrated circuit architecture that enables enhanced data processing through distinct circuit connections on a semiconductor wafer, allowing for direct communication between multiple dies on a single substrate, along with the use of an elastomeric connector to manage thermal expansion mismatch and secure the large silicon die to a PCB, and a method for precise fabrication of orifices and uniform compression systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple distinct photomasks are used to fabricate different circuit connections, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvecircuit connection fabrication precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into distinct stages, each handling specific types of circuit connections. First photomasks fabricate intra-die connections within individual dies, while second photomasks fabricate inter-die connections between dies. This segmentation allows each photomask to be optimized for its specific function, improving manufacturing precision without requiring all connection types to be fabricated simultaneously with a single complex photomask.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Intra-die connections are fabricated in advance using first photomasks before the dies are separated and repositioned. This preliminary action allows the intra-die circuitry to be completed and verified before the more complex inter-die connection fabrication using second photomasks, thereby improving overall manufacturing precision through staged optimization.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple photomask fabrication steps are implemented, then manufacturing precision improves, but productivity decreases

Engineering Contradiction:
Improvecircuit connection fabrication precisionVSAvoidfabrication throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The fabrication process is divided into parallel tracks: first photomasks operate on individual dies to create intra-die connections, while second photomasks operate on the repositioned dies to create inter-die connections. This segmentation allows different connection types to be fabricated simultaneously in different locations, improving productivity while maintaining the precision benefits of specialized photomasks for each connection type.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If intra-die and inter-die connections are fabricated separately, then manufacturing precision is improved, but loss of time increases

Engineering Contradiction:
Improveconnection fabrication precisionVSAvoidfabrication cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Intra-die connections are fabricated as a preliminary action using first photomasks before die separation and repositioning. This allows the intra-die circuitry to be completed in advance, so that when second photomasks fabricate inter-die connections later, both processes can be optimized independently for precision without requiring sequential completion of all connection types.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fabrication process maintains continuity by overlapping operations: while first photomasks are fabricating intra-die connections on one set of dies, second photomasks can simultaneously fabricate inter-die connections on repositioned dies. This continuous utilization of fabrication equipment reduces overall cycle time while preserving the precision advantages of separate specialized photomasks.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances data processing efficiency, reduces communication latency, and addresses thermal expansion mismatch issues, enabling the creation of larger, more powerful computer chips that can efficiently handle AI and machine learning tasks while maintaining system integrity.

Implementation Method 1

use of an elastomeric connector to manage thermal expansion mismatch

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

use of an elastomeric connector to manage thermal expansion mismatch

Methodology Applied
Scientific EffectElasticity: Elasticity

Implementation Method 3

fabricating, using a first photomask, a plurality of a first type of circuit connections

Methodology Applied
Scientific EffectPhotoexposure: Photography

Data Source

PatentUS10923456B2Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die
Publication Date: 2021.02.16 CEREBRAS SYSTEMS INC
  • US10923456B2 patent drawing
  • US10923456B2 patent drawing
  • US10923456B2 patent drawing

AI summary

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.