Integrated Circuit Electrolytic Deposition for High-Quality Inductors
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Solution Overview
Problem
Current methods for manufacturing integrated circuits with high-quality passive components and interconnections are inefficient due to the need for multiple technological steps and sensitivity to substrate dielectric quality, particularly in silicon substrates with low resistivity, which results in significant losses and poor quality factors for inductors.
Innovation Solution
A method that involves depositing a dielectric layer with undercut flanks, followed by simultaneous electrolytic deposition of the electrical structure on both the surface and sidewalls of the dielectric layer, allowing for the formation of continuous metal lines and interconnections in a single step, reducing the number of technological steps and mechanical stress on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple technological steps are used to form electrical structures through thick dielectric layers, then the electrical performance and quality factor of passive components are improved, but the manufacturing complexity and number of technological steps increase significantly
Solution Approach 1:
The patent combines the formation of multiple electrical structures at different levels into a single electrolytic deposition step. By preparing the substrate with multiple metallization layers (first metallization layer on the substrate, second metallization layer on the dielectric layer) before the electrolytic deposition, the process simultaneously creates vertical interconnections through the dielectric layer and horizontal interconnection structures on the surface, eliminating the need for sequential deposition steps for each level.
Solution Approach 2:
The patent performs preliminary preparation of the substrate by depositing multiple metallization layers (bonding layer, first metallization layer, second metallization layer) and forming the dielectric layer with its specific flank geometry before the actual electrolytic deposition. This preliminary structuring enables the subsequent single-step electrolytic deposition to achieve complex multi-level electrical structures that would otherwise require multiple sequential steps.
2Reliability
If thick metal levels are implemented to reduce losses in passive components, then the quality factor of inductors is improved, but the manufacturing process complexity and number of steps increase
Solution Approach 1:
The patent merges the formation of thick metal interconnection structures with the formation of dielectric layers and vertical interconnections into a single electrolytic deposition process. The electrolytic deposition simultaneously creates thick conductive paths that reduce losses while maintaining simple manufacturing, as the thick metal levels are formed in the same step as the vertical interconnections through the dielectric layer.
3Reliability
If multiple interfaces between metallic levels are created, then the electrical performance is improved, but the mechanical stress on the substrate increases
Solution Approach 1:
The patent merges the formation of multiple metallic levels and their interfaces into a single continuous electrolytic deposition process. This creates a monolithic electrical structure where multiple metallic levels are formed simultaneously from the same material source, reducing thermal and mechanical stress that would arise from multiple separate deposition processes and subsequent cooling cycles.
4Ease of manufacture
If conventional electrolytic deposition methods are used with flanks, then the electrical structure is formed, but the deposition quality is poor due to shadowing effects and irregularities
Solution Approach 1:
The patent performs preliminary formation of the dielectric layer with specifically engineered flanks that have controlled geometry (height greater than 10 μm, with undercut profiles). This preliminary structuring creates optimal conditions for the subsequent electrolytic deposition by ensuring that the flanks are properly prepared and positioned, allowing the electrolyte to access all surfaces uniformly and eliminating shadowing effects that would otherwise cause deposition irregularities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance and mechanical robustness of the integrated circuits by reducing interfaces between metallic levels, improving the quality factor of passive components, and minimizing losses, while simplifying the manufacturing process and reducing costs.
Implementation Method 1
the electrical structure is formed by depositing the electrically conductive material by simultaneously depositing the structural element on the upper surface of the dielectric layer and the interconnection element on the sidewall
Data Source
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AI summary
The invention relates to a method for manufacturing an integrated circuit, said method including the steps of: forming at least one dielectric layer (15) above an upper surface of a substrate (5), wherein said dielectric layer extends over an underlying surface (12), the dielectric layer (15) having an upper surface (25) and a flank (40) that extends between the upper surface (25) and the underlying surface (12); and forming an integral electrical structure (70) made of an electrically conductive material, including a structural element (75) extending over the upper surface (25) of the dielectric layer (15) and an interconnection element (80) extending from the structural element (75) along the flank (40) up to the underlying surface (12). According to one aspect of the invention, the flank (40) has a height of more than 10 μm, and the electrical structure (70) is formed by depositing electrically conductive material, while simultaneously depositing the structural element (75) on the upper surface (25) of the dielectric layer (15) and the interconnection element (80) on the flank (40).