IC Embedded Substrate with Segmented Insulating Layers

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Solution Overview

Problem

Conventional IC embedded substrates face challenges in reducing the size of via-hole conductors and narrowing their pitch due to the similar thickness of the core substrate and IC chip, leading to instability and connection issues, especially when the insulating layer's filler size exceeds the resin thickness, affecting adhesive strength and wiring reliability.

Innovation Solution

The IC embedded substrate design features a core substrate with an opening housing the IC chip, where the upper insulating layer fills the gap between the IC chip and the core substrate's inner peripheral surface, reducing the distance from the IC chip to the upper insulating layer, allowing for smaller via-hole conductors and narrower pitches, while maintaining high substrate strength and preventing dust accumulation on the IC chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the insulating layer thickness is reduced to decrease via-hole conductor size and narrow pitch, then the via-hole conductor diameter can be reduced and pitch narrowed, but the adhesive strength of the insulating layer deteriorates and wiring reliability decreases

Engineering Contradiction:
Improvevia-hole conductor size and pitchVSAvoidadhesive strength and wiring reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The insulating layer is divided into two separate layers: a first insulating layer covering the core substrate and a second insulating layer covering the IC chip. This segmentation allows each layer to be optimized independently - the first layer can be thicker for adhesive strength while the second layer can be thinner for via-hole size reduction, resolving the contradiction between via-hole pitch and reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the insulating structure are given different thicknesses and properties. The first insulating layer has greater thickness for adhesive strength, while the second insulating layer has reduced thickness for via-hole conductor size. This local differentiation allows simultaneous optimization of both via-hole pitch and reliability

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the area of the cavity is reduced to expand the effective area of the core substrate, then the effective area increases, but the gap between the IC chip and cavity inner peripheral surface becomes too narrow for sufficient resin filling

Engineering Contradiction:
Improveeffective area of core substrateVSAvoidresin filling capability
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The cavity inner peripheral surface is pre-treated with a roughening coating before mounting the IC chip. This preliminary action creates a textured surface that enhances resin flow and filling capability in the narrow gap between the IC chip and cavity wall, enabling sufficient resin penetration even when the cavity area is minimized for maximum effective area

Inventive Principle:
Principle #10Preliminary action

3Strength

If the core substrate thickness is made equal to the IC chip thickness to ensure substrate strength, then the substrate maintains high strength, but the distance from IC chip to insulating layer becomes long requiring larger via-hole conductors

Engineering Contradiction:
Improvesubstrate strengthVSAvoidvia-hole conductor size
Core Design Contradiction:
StrengthVSEase of operation

Solution Approach 1:

The insulating structure is extended into a third dimension by adding a second insulating layer on top of the IC chip. This vertical extension allows the via-hole conductors to connect to the second insulating layer at a shorter distance, reducing via-hole diameter requirements while the core substrate maintains its original thickness for structural strength

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9153553B2IC embedded substrate and method of manufacturing the same
Publication Date: 2015.10.06 TDK CORP
  • US9153553B2 patent drawing
  • US9153553B2 patent drawing
  • US9153553B2 patent drawing

AI summary

Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The upper insulating layer is formed in such a way as to fill a gap between a side surface of the IC chip and an inner peripheral surface of the opening of the core substrate. A first distance from the upper surface of the IC chip to an upper surface of the upper insulating layer is shorter than a second distance from the upper surface of the core substrate to the upper surface of the upper insulating layer.