IC Emission Obfuscation via Threshold Voltage and Placement
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Solution Overview
Problem
Integrated circuit designs face security vulnerabilities due to unauthorized access through emission-based side-channel detection techniques, particularly in the IC supply chain, where untrusted entities can detect internal states and secret keys using advanced probing methods.
Innovation Solution
The implementation of emission obfuscation optimizations in integrated circuit design, which involves identifying obfuscation indicators, marking relevant logic elements, and applying optimizations such as special placement, threshold voltage adjustments, and path-based modifications to obscure emissions from side-channel detection, thereby securing the secret key path and preventing unauthorized access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic locking techniques are applied to secure integrated circuit designs, then design protection against reverse engineering is improved, but the circuit becomes vulnerable to emission-based side channel detection attacks
Solution Approach 1:
The patent applies parameter changes by modifying the physical characteristics of logic elements through threshold voltage adjustments (using high-Vt vs low-Vt cells) and placement strategies. These parameter changes alter the emission profiles of logic elements to obfuscate the secret key path, making emission-based side channel detection ineffective while maintaining the security benefits of logic locking
Solution Approach 2:
The patent introduces intermediary logic elements and buffer cells between the secret key storage and the locked logic. These intermediary elements act as mediators that disrupt the direct emission signal path, preventing attackers from directly observing the secret key through emission-based detection while the secret key still functions correctly for unlocking the circuit
2Reliability
If additional logic elements are added for logic locking, then intellectual property protection is improved, but device complexity increases
Solution Approach 1:
The patent merges the emission obfuscation functionality with the existing logic locking structure by integrating threshold voltage assignments and placement constraints into the logic locking design flow. This combining approach achieves dual functionality (security + emission protection) without requiring completely separate circuit structures, thereby limiting the increase in device complexity
3Reliability
If emission obfuscation optimizations are applied to marked logic elements, then protection against side channel detection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by identifying and marking the secret key path logic elements during the design phase, before fabrication. The emission obfuscation optimizations (threshold voltage assignments, placement constraints) are predetermined and encoded in the netlist, allowing standard fabrication processes to be used without requiring complex post-manufacturing adjustments or specialized manufacturing equipment
Data Source
AI summary
Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.