Non-destructive State Visualization in IC Emulation
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Solution Overview
Problem
The increasing complexity of integrated circuit designs and the high costs associated with verifying gate-level representations before manufacturing, where traditional gate-level timing simulation is time-consuming and hardware emulation provides a faster alternative but requires efficient state visualization techniques to debug and optimize circuit designs.
Innovation Solution
Implementing a computer system that uses observable and non-observable storage circuits in integrated circuits, where observable storage circuits are accessible via scan chains, allowing for the extraction of state data from both types of storage circuits without disturbing the data, enabling efficient debugging and optimization of circuit designs through hardware emulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-level timing simulation is used to verify circuit design, then verification thoroughness is improved, but execution time increases significantly
Solution Approach 1:
The patent creates a hardware copy (emulator) of the circuit design that replicates the functionality of the gate-level representation. This hardware copy executes verification tests much faster than software simulation while maintaining verification thoroughness, directly resolving the time-consuming nature of gate-level timing simulation.
Solution Approach 2:
The patent replaces the software-based gate-level timing simulation system with a hardware-based emulation system. This substitution transitions from a software model executing on a computer to a physical hardware implementation, enabling parallel processing and significantly reducing verification execution time.
2Loss of time
If hardware emulation is used to verify circuit design, then execution time is reduced, but state visualization capability is limited
Solution Approach 1:
The patent introduces scan chains as intermediary structures that connect the internal storage elements of the hardware emulator to external observation points. These scan chains enable the test bench to read and visualize the state of internal registers and storage elements without disrupting normal circuit operation, thus providing complete state visibility in the hardware emulation environment.
Solution Approach 2:
The patent segments the internal storage elements of the hardware emulator into accessible units connected through scan chains. By dividing the internal state into discrete, accessible segments that can be individually observed and controlled, the system enables comprehensive state visualization while maintaining the speed advantages of hardware emulation.
3Ease of operation
If scan chains are used to access storage circuits, then state accessibility is improved, but circuit complexity increases
Solution Approach 1:
The patent designs the scan chain structure to serve multiple functions: it enables state visualization, provides test access, and maintains normal circuit operation. This multi-functional approach allows the same hardware structures to be used for both operational and diagnostic purposes, reducing the need for separate dedicated test infrastructure and offsetting the added complexity.
Data Source
AI summary
An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits. The local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.