Integrated Circuit Equivalency Analysis Using Statistical Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for determining the equivalency of integrated circuits (ICs) fabricated before and after process changes are prone to false positives and false negatives, leading to inaccurate assessment of IC quality and potential defects in production.
Innovation Solution
The method involves dividing data into control and experimental subsets, summarizing statistics to an experimental unit above a site level, and performing a two-way analysis of variance (ANOVA) or Kruskal-Wallace Test to determine equivalency, respecting variations among wafers or lots and providing statistical significance for accurate evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional equivalency analysis methods are used to compare IC characteristics before and after process changes, then the assessment of IC quality can be performed, but false positives and false negatives occur leading to inaccurate assessment of IC quality and potential defects in production
Solution Approach 1:
The patent transforms the equivalency analysis from a simple overlap comparison of scattered distributions to a rigorous statistical hypothesis testing framework. By changing the analytical parameters from visual/qualitative overlap assessment to quantitative statistical tests (ANOVA, t-tests, F-tests) with defined significance levels, the method achieves both high measurement precision and reliability in IC quality assessment
Solution Approach 2:
The patent replaces the conventional mechanical/visual approach of comparing scattered characteristic distributions with a systematic statistical testing methodology. Instead of manually assessing overlap extents, the invention employs automated statistical tests that objectively determine equivalency based on predetermined significance thresholds, eliminating human subjectivity and improving both precision and reliability
2Reliability
If split lots are used to analyze equivalency by comparing characteristics of base set and test set ICs, then equivalency can be assessed, but the process becomes complex and time-consuming
Solution Approach 1:
The patent implements preliminary action by establishing comprehensive statistical testing protocols and significance thresholds before the equivalency analysis begins. By pre-defining the statistical framework, test parameters, and decision criteria, the method eliminates time-consuming post-hoc analysis and iterative adjustments, streamlining the overall process while maintaining high reliability
Solution Approach 2:
The invention changes the analytical parameters from extensive manual comparison of scattered data points to focused statistical tests that evaluate specific hypotheses. This parameter transformation reduces the effective dimensionality of the analysis, maintaining reliability while significantly reducing the time required for equivalency determination
3Ease of manufacture
If extreme values or outliers are disregarded in equivalency analysis, then the comparison becomes simpler, but the accuracy of equivalency determination is reduced
Solution Approach 1:
The patent extracts outliers from the data set for separate handling rather than simply disregarding them. By isolating extreme values and applying specific statistical tests to evaluate their impact, the method maintains analytical simplicity while preserving measurement accuracy. The extracted outliers are evaluated through formal statistical criteria rather than arbitrary exclusion
Solution Approach 2:
The invention introduces statistical significance testing as an intermediary mechanism between the raw data including outliers and the final equivalency determination. This intermediary layer systematically evaluates the impact of extreme values through formal tests, maintaining both process simplicity and measurement accuracy by providing an objective criterion for handling outliers
Data Source
AI summary
Methods of analyzing equivalency with respect to split and limited release lots of wafers of integrated circuits. One embodiment of the split-lot method includes: (1) dividing a set of data regarding the split lot into control and experimental subsets, (2) summarizing statistics regarding the set and the subsets to an experimental unit above a site level and (3) performing a two-way analysis of variance with respect to the statistics to determine the equivalency, using the set for one way of the analysis of variance and the subsets for another way of the analysis of variance. One embodiment of the limited-release method includes: (1) designating a set of data regarding a lot fabricated by a normative integrated circuit fabrication process as a control set, (2) designating a set of data regarding the limited release lot as an experimental set, (3) summarizing statistics regarding the control and experimental sets to an experimental unit above a site level and (4) performing a Kruskal-Wallace test with respect to the statistics to determine the equivalency.