Integrated Circuit Error Protection Analysis via Storage Cell Grouping
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Solution Overview
Problem
As integrated circuits shrink, they become more susceptible to radiation-induced faults like single-event upsets (SEUs) and multi-bit upsets (MBUs), which existing error detection and correction mechanisms struggle to effectively manage, leading to reliability concerns and inefficient verification processes during logic implementation.
Innovation Solution
An automated method for grouping storage cells into checking groups within an integrated circuit design, using structural and textual analysis to assign unique identifiers and optimize error protection, thereby reducing the number of unnecessary error checkers and improving error control mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error detection and correction mechanisms are used in shrunk integrated circuits, then radiation-induced faults can be detected, but the mechanisms become inefficient and cannot effectively manage multi-bit errors
Solution Approach 1:
The patent segments storage cells into distinct checking groups, where each group is monitored by a dedicated error checker. This segmentation allows the system to efficiently handle radiation-induced faults by localizing error detection to specific groups, avoiding the inefficiency of comprehensive mechanisms while maintaining effectiveness against multi-bit errors through targeted monitoring.
2Reliability
If comprehensive error control mechanisms are implemented, then reliability improves, but verification process becomes inefficient and overhead increases
Solution Approach 1:
The patent performs preliminary grouping of storage cells into checking groups during the design phase, assigning unique identifiers to each group before implementation. This preliminary organization enables efficient verification processes, as the grouping structure is pre-established and can be directly used for error protection analysis without requiring complex runtime verification mechanisms.
Solution Approach 2:
The patent creates a simplified representation of error checking relationships through the grouping structure, where each checking group is characterized by its unique identifier and associated storage cells. This copied structure allows for efficient verification and analysis without requiring complete simulation of the actual error detection processes, reducing overhead while maintaining verification effectiveness.
3Reliability
If error checkers are added to protect against radiation faults, then reliability improves, but the number of unnecessary error checkers increases overhead
Solution Approach 1:
The patent applies local quality by assigning error checking capabilities selectively to specific checking groups based on their vulnerability to radiation-induced faults. Rather than uniformly distributing error checkers throughout the circuit, the grouping structure allows concentrated protection where needed, reducing the total number of error checkers while maintaining effective radiation fault protection in critical areas.
Data Source
AI summary
Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.