Power Supply Equalization Circuit for IC ESD Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuits face challenges in accommodating a wide range of power supply voltages and protecting against electrostatic discharge (ESD) due to variations in breakdown voltage of diodes and the need for multiple shunt circuits, which complicates design and manufacturing, especially as devices become smaller.
Innovation Solution
A protection circuit using low-stress voltage devices with a voltage drop network and shunt circuits, including an RC trigger stage and NMOS shunt stage, coupled through a PMOS equalization device to manage high voltage and ESD events, minimizing the number of shunt devices required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple isolated shunt circuits are used for different voltage levels, then protection coverage is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple shunt circuits for different voltage levels (3.3V and 1.8V) into a single integrated protection circuit. The shared shunt transistor Qp and equalization transistor Qe allow one protection circuit to serve multiple voltage domains, reducing the total number of components while maintaining comprehensive protection coverage across all voltage levels.
Solution Approach 2:
The protection circuit is designed with multi-functional capability to handle both 3.3V and 1.8V voltage levels using the same basic circuit topology. The equalization transistor Qe enables the circuit to adaptively equalize voltage potentials between different domains, allowing a universal protection mechanism to serve multiple specific voltage protection needs.
2Object-affected harmful factors
If diode breakdown voltage is used for protection, then ESD protection is provided, but voltage variation due to design and fabrication reduces reliability
Solution Approach 1:
The patent introduces an equalization transistor Qe as an intermediary element between the 3.3V and 1.8V shunt circuits. This mediator transistor actively equalizes the voltage potentials between different voltage domains, compensating for variations in diode breakdown voltages and ensuring consistent protection behavior across different fabrication processes and design variations.
Solution Approach 2:
The circuit dynamically adjusts operating parameters by using the equalization transistor to modify voltage distribution across the protection circuit elements. By changing the effective voltage parameters through active equalization rather than relying on fixed breakdown voltages, the circuit achieves more consistent protection performance despite manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects low voltage transistors and circuits from excessive power supply levels and ESD events, providing higher ESD tolerance and efficiency while reducing the complexity and size of the IC circuitry.
Implementation Method 1
The trigger circuits are configured to activate the shunt transistors in response to a rate of rise of voltage
Implementation Method 2
coupled through an equalization device that comprises a PMOS transistor placed in series between pairs of shunt circuits
Implementation Method 3
Present protection circuits typically utilize reverse-biased diodes acting as avalanche breakdown clamps to limit the voltage between the power supply terminals of the IC
Data Source
AI summary
Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.