IC Extension Pad Structure for Wafer Sawing Stress Management
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Solution Overview
Problem
Integrated circuits (ICs) face chip cracking issues during the wafer sawing process due to the inability to effectively transfer cutting stress, which is exacerbated by the miniaturization demands and novel packaging requirements.
Innovation Solution
An integrated circuit design featuring an extension pad structure with a via-free region between the bonding pad structure and the scribe line, allowing stress transfer to the bonding pad structure, thereby preventing chip cracking. This design includes a scribe line, a bonding pad structure with multiple metal layers and vias, and an extension pad structure with fewer metal layers and vias, specifically a via-free region adjacent to the scribe line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor manufacturing processes are used without extension pad structure, then manufacturing process is simple, but chip cracking occurs during wafer sawing process
Solution Approach 1:
The pad structure is segmented into bonding pad structure and extension pad structure, with the extension pad structure containing a via-free region that segments the stress path during wafer sawing, preventing crack propagation while maintaining structural integrity
Solution Approach 2:
The extension pad structure acts as an intermediary element between the bonding pad structure and the scribe line, transferring cutting stress away from critical bonding pads through its via-free region, thereby preventing chip cracking
2Volume of moving object
If miniaturization is pursued without novel packaging process, then device size is reduced, but chip cracking issues are exacerbated
Solution Approach 1:
The extension pad structure introduces local quality variation by creating a via-free region in specific locations, allowing stress to be locally managed during wafer sawing while maintaining overall device miniaturization
Data Source
AI summary
An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region.