Integrated Circuit Fabrication via Parallel Substrate Segmentation
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Solution Overview
Problem
The increasing density of integrated circuits and the need for more interconnect layers lead to higher probabilities of defects and particles during back-end-of-line processes, resulting in lower yields and longer cycle times due to the serial nature of front-end-of-line and back-end-of-line processing.
Innovation Solution
The solution involves fabricating front-end-of-line and back-end-of-line processing layers in parallel, using separate substrates for each, where the first substrate contains active devices and front-end-of-line layers, and the second substrate contains interconnect structures and through-silicon vias, with bump pads connecting them, allowing for independent handling of defects and reducing cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If more interconnect layers are formed to increase integrated circuit density, then the manufacturing precision and reliability deteriorate due to higher probability of defects and particles during back-end-of-line processes
Solution Approach 1:
The patent divides the integrated circuit fabrication into two separate substrates: first substrate for front-end-of-line processes and second substrate for back-end-of-line processes. This segmentation allows independent processing and defect handling for each substrate, preventing defects in interconnect layers from affecting the entire circuit yield.
2Manufacturing precision
If front-end-of-line and back-end-of-line processes are performed in series, then the manufacturing precision is maintained, but the production cycle time increases and yield decreases due to defect propagation
Solution Approach 1:
The patent segments the fabrication process into parallel streams on separate substrates, allowing front-end-of-line and back-end-of-line processes to proceed simultaneously without serial dependency, thereby reducing cycle time while maintaining defect control through separate handling.
Solution Approach 2:
The patent performs preliminary separation of front-end-of-line and back-end-of-line processes onto different substrates before final assembly, enabling independent optimization and defect management for each process stream, which reduces overall cycle time while maintaining precision.
3Manufacturing precision
If more interconnect layers are formed to satisfy miniaturization requirements, then the area is reduced and density increases, but the probability of defects and particles increases leading to lower yield
Solution Approach 1:
The patent segments the circuit fabrication into separate substrates for front-end and back-end processes, allowing high-density interconnect layers to be formed on the second substrate without compromising overall yield, as defects in this substrate do not propagate to the first substrate containing active devices.
Data Source
AI summary
An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.