Integrated Circuit Fault Detection via OR-Gate Daisy Chains
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Solution Overview
Problem
Conventional systems for high assurance specifications, such as Fail Safe Design Assurance, are inefficient due to the need for redundant devices to detect faults, which increases system size, power consumption, weight, and cost, and fail to adequately ensure reliability of critical signal lines.
Innovation Solution
The implementation of fault detection circuitry in integrated circuit devices that monitors signals at the endpoints of signal trees using OR-gate daisy chains and sensors to generate fault detection signals, with mechanisms to assure the reliability of the fault detection circuitry itself, allowing for efficient fault handling procedures like device reset or cryptographic key deletion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate devices are used to monitor critical signals and provide fault detection, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple fault detection functions into a single integrated circuit device. The device includes a processor that executes instructions to monitor multiple critical signals, determine faults, and initiate handling procedures. This merging approach maintains reliability by providing comprehensive fault detection while reducing device complexity compared to using multiple separate monitoring devices.
Solution Approach 2:
The integrated circuit device performs multiple functions: monitoring critical signals, determining faults in those signals, and initiating fault handling procedures. This multi-functional approach allows a single device to replace what would traditionally require multiple specialized devices, thereby improving reliability without proportionally increasing system complexity.
2Reliability
If redundant devices are used to detect faults in critical signals, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent consolidates fault detection functionality into a single integrated circuit device that monitors multiple critical signals simultaneously. This approach maintains the reliability benefits of redundant monitoring while significantly reducing power consumption compared to running multiple separate monitoring devices.
Solution Approach 2:
The integrated circuit device includes a processor that automatically monitors critical signals, determines faults, and initiates fault handling procedures without requiring external monitoring systems. This self-service capability eliminates the need for additional redundant devices that would consume extra power.
3Reliability
If multiple devices are used to provide fault detection, then reliability is improved, but device size increases
Solution Approach 1:
The patent integrates multiple fault detection functions into a single integrated circuit device, eliminating the need for multiple separate devices. The device includes a processor and memory that work together to monitor critical signals and implement fault handling, thereby maintaining reliability while reducing the physical area required.
4Reliability
If separate monitoring devices are used, then fault detection capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple fault detection functions into a single integrated circuit device that can be manufactured as one unit. This approach maintains comprehensive fault detection capability while reducing manufacturing costs associated with assembling and testing multiple separate devices.
Data Source
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AI summary
Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.