Integrated Circuit Fault Diagnosis via Checkpoint Segmentation
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Solution Overview
Problem
Current diagnostic techniques for integrated circuits, especially for large chips, face challenges such as excessively long simulation run times, high memory requirements, and low diagnostic resolution, which can lead to ineffective physical and electrical failure analysis due to incomplete fault models and unmodeled fault types like path delay and bridging faults.
Innovation Solution
The method involves executing functional test exercisers in a sequence up to checkpoints, using built-in structural test support circuits to identify likely causes of failure, and iteratively invoking portions of the execution sequence between checkpoints to progressively isolate the most likely failure source, combining results from structural test support circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cause-effect analysis techniques with fault dictionaries are used for large chips, then fault diagnosis can be performed, but simulation run time becomes excessively long and memory requirements become prohibitively large
Solution Approach 1:
The patent segments the fault diagnosis process by dividing the chip into functional blocks with checkpoints. Instead of simulating the entire chip simultaneously, the system executes test patterns up to specific checkpoints and uses structural test support circuits to analyze failures locally. This segmentation reduces the simulation scope and time while maintaining diagnostic reliability.
Solution Approach 2:
The patent introduces structural test support circuits as intermediaries between the functional test exercisers and the fault analysis process. These circuits capture and analyze failure data at checkpoints, providing summarized failure information that reduces the computational burden on the main simulation system while maintaining diagnostic accuracy.
2Reliability
If cause-effect analysis techniques with fault dictionaries are used for large chips, then fault diagnosis can be performed, but memory requirements become prohibitively large
Solution Approach 1:
The patent extracts failure analysis functionality from the main simulation system and places it in dedicated structural test support circuits. These circuits capture only the essential failure data at checkpoints, separating the bulk of the simulation data from the diagnostic process and reducing overall memory requirements while maintaining diagnostic capability.
3Productivity
If effect-cause algorithms are used for fault diagnostics, then processing resource requirements are reduced, but fault candidates can be wrong or there can be too many candidates with low scores
Solution Approach 1:
The patent implements feedback mechanisms where structural test support circuits continuously analyze failure data and provide results back to the functional test exercisers. This feedback loop enables the system to refine fault candidates based on actual failure observations, improving accuracy while maintaining the efficiency of effect-cause analysis.
Solution Approach 2:
The patent performs preliminary actions by executing test patterns to specific checkpoints before full failure analysis. The structural test support circuits prepare and pre-analyze failure data at these intermediate points, allowing the main diagnostic algorithm to work with pre-processed information, thereby improving both speed and accuracy.
4Productivity
If incomplete fault models are used, then diagnostic software can run faster, but fault candidates become less accurate due to unmodeled fault types
Solution Approach 1:
The patent changes the approach from using comprehensive but slow fault models to using structural test support circuits that dynamically analyze failure patterns. This parameter change in the diagnostic methodology allows the system to adapt to various fault types without requiring pre-computed fault models, maintaining speed while improving accuracy through real-time structural analysis.
Data Source
AI summary
Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.