Integrated Circuit Fill Structures for Uniform Layer Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for achieving uniform layer density in integrated circuits, such as the use of dummy or fill structures, often result in sub-optimal calculation times and unpredictable electrical effects, leading to non-uniformity and potential timing problems, especially in complex layers like the first metal layer.
Innovation Solution
Configuring fill structures as part of the initial cell library layout, allowing for optimized placement and removal of conflicting fill structures during interconnect wiring, thereby improving uniformity and reducing computational effort.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If automated fill algorithms are used to achieve uniform layer density, then calculation time is reduced, but fill layout quality becomes sub-optimal and electrical effects become unpredictable
Solution Approach 1:
The patent applies preliminary action by pre-configuring fill structures as part of the cell library before the actual circuit layout is generated. This allows the fill structures to be optimized in advance for their intended purpose of achieving uniform layer density, while the actual circuit layout can be generated quickly by simply instantiating these pre-configured cells. This resolves the contradiction by performing the computationally intensive fill optimization once during cell library creation rather than repeatedly during each circuit layout generation.
Solution Approach 2:
The patent segments the fill structure configuration into discrete cell-level units that can be independently optimized and stored in a library. Each cell in the library contains pre-calculated optimal fill structures for achieving uniform density. When generating a full circuit layout, the system simply combines these pre-segmented cell units, dramatically reducing the overall calculation time while maintaining high fill layout quality.
2Manufacturing precision
If fill structures are added to achieve uniform layer density, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the cell library universal by creating a reusable set of pre-configured cells that each contain optimized fill structures. These cells can be instantiated multiple times in different circuit layouts to achieve uniform layer density. This multi-functional approach allows the same pre-optimized fill configurations to serve multiple purposes across different circuit designs, improving layer density uniformity without proportionally increasing complexity.
Solution Approach 2:
The patent utilizes parameter changes by allowing flexible configuration of fill structures within the cell library based on different design requirements. The pre-configured cells can be adapted by adjusting parameters such as fill material composition, density, and spatial distribution to achieve the desired layer uniformity for specific applications, while maintaining the overall simplicity of the cell-based architecture.
3Manufacturing precision
If manual layout methods are used for fill structures, then fill layout quality is optimized, but calculation time and computational cost increase significantly
Solution Approach 1:
The patent applies copying by creating a library of pre-optimized cell units that can be replicated and instantiated throughout the circuit layout. Instead of manually creating fill structures for each unique location, the system copies and adapts the pre-optimized cell designs from the library. This dramatically reduces computational time while maintaining high fill layout quality, as the complex optimization work has already been performed once during cell library creation.
Data Source
AI summary
A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there between, and configuring and positioning a plurality of fill structures in the gaps. The method further includes arranging selected logic cells from the cell library to form a desired layout of the integrated circuit, routing interconnect wiring between the selected logic cells in the at least one layer, and removing fill structures at positions that conflict with the routing of the interconnect wiring.