Automated IC Floor Plan Generation with Macro Placement Optimization
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Solution Overview
Problem
Current electronic design automation (EDA) tools lack support for fine-grain module planning, macro pin orientation, channel space optimization, and fine-grain dataflow placement, relying heavily on manual efforts and designer skills, which limits efficiency and flexibility in generating feasible integrated circuit floor plans.
Innovation Solution
A system and method that automates the generation of integrated circuit floor plans through stages such as IC design planning, auto I/O placement, module planning, macro placement, alignment, orientation optimization, channel resource detection, macro legalization, and dataflow macro adjustment, using machine learning and path-tracing algorithms to optimize routability and reduce manual intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual floorplanning methods are used, then designer control and flexibility are maintained, but productivity and design implementation turnaround time deteriorate
Solution Approach 1:
The floorplanning system performs self-service by automatically generating multiple floor plan candidates, optimizing macro placements, and selecting optimal solutions without requiring continuous manual intervention. The system autonomously executes floorplanning operations including macro placement optimization, channel resource detection, and dataflow macro adjustment, significantly improving productivity while reducing design implementation turnaround time
Solution Approach 2:
The system performs preliminary actions by pre-generating multiple floor plan candidates with different macro placements and configurations before final selection. This includes preliminary macro placement optimization, channel resource detection, and dataflow analysis, allowing designers to evaluate multiple options and select the best solution, thereby improving both productivity and decision quality
2Productivity
If automated floorplanning tools are used, then productivity is improved, but manufacturing precision and rule compliance deteriorate
Solution Approach 1:
The system implements feedback mechanisms by continuously detecting channel resources, analyzing routing congestion, and adjusting macro placements to maintain design rule compliance. The automated floorplanning tool monitors placement quality, detects routing conflicts, and performs iterative optimizations to ensure manufactured precision is maintained while improving productivity through automation
Solution Approach 2:
The system employs dynamic adjustments by continuously optimizing macro placements based on detected channel resources and routing requirements. The floorplanning tool dynamically repositions macros, adjusts channel widths, and modifies placements to maintain design rule compliance throughout the automated process, ensuring manufacturing precision is preserved while achieving high productivity
3Reliability
If fine-grain module planning and macro pin orientation optimization are implemented, then routing quality improves, but device complexity increases
Solution Approach 1:
The system applies segmentation by dividing the floorplanning process into distinct stages: macro placement optimization, channel resource detection, dataflow macro adjustment, and routing quality assessment. This segmented approach handles fine-grain module planning and macro pin orientation optimization in manageable segments, improving routability while controlling the complexity of the overall floorplanning process through structured decomposition
Data Source
AI summary
A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.