IC Floor Plan Tile Segmentation for Area Minimization
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Solution Overview
Problem
The existing methods for optimizing the layout area of integrated circuits (ICs) during the design process often result in increased chip size due to congestion, leading to higher manufacturing costs and inefficiencies in channel routing and partition re-shaping.
Innovation Solution
A method that utilizes a computer-aided design approach to re-shape partitions and re-route nets within channels by changing the properties of tiles between partitions and channels, based on routing densities and flexible spaces, to minimize the layout area of ICs, employing a combination of tile segmentation, homogenization, and linear programming to optimize the floor plan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing methods are used to optimize layout area, then design process is simplified, but chip size increases due to congestion
Solution Approach 1:
The floorplan is segmented into a grid of tiles, where each tile represents a discrete unit that can be independently classified as partition or channel. This segmentation enables fine-grained control over the layout structure, allowing the optimization algorithm to adjust individual tiles to reduce congestion while minimizing chip size.
Solution Approach 2:
The tile properties are made dynamic and changeable during the optimization process. The system can flip tiles between partition and channel states, and adjust partition shapes by modifying tile assignments, enabling the layout to adapt dynamically to routing density requirements and congestion patterns.
2Productivity
If channel routing is optimized, then routing efficiency improves, but partition shape becomes constrained
Solution Approach 1:
Partition shapes are represented as flexible configurations of tiles rather than fixed geometric forms. The optimization algorithm can dynamically adjust partition boundaries by flipping adjacent tiles between partition and channel states, allowing partitions to reshape themselves to accommodate routing efficiency requirements while maintaining logical functionality.
Solution Approach 2:
Different regions of the floorplan can have different tile configurations optimized for their specific routing needs. Channels with high routing density can be widened by converting adjacent partition tiles to channel tiles locally, while regions with lower density maintain tighter partition boundaries, creating a non-uniform but optimized overall structure.
3Area of stationary object
If partition re-shaping is performed, then layout area decreases, but routing complexity increases
Solution Approach 1:
The re-shaping process operates on individual tiles rather than entire partitions, breaking down the complex re-shaping operation into manageable unit transformations. Each tile flip is a simple, localized change that can be evaluated and executed independently, reducing the overall computational complexity compared to global re-shaping approaches.
Solution Approach 2:
The system performs preliminary routing analysis to determine routing densities in different channel regions before executing re-shaping operations. This preliminary assessment allows the optimization algorithm to plan re-shaping moves that reduce layout area while anticipating and preparing for the routing adjustments needed, thereby managing routing complexity proactively rather than reactively.
Data Source
AI summary
A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels.