IC Floorplan Stitching with Relaxed Critical Dimensions
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Solution Overview
Problem
The complexity of at-resolution stitching in high-NA EUVL scanners necessitates nanometer-order precision for optical proximity correction and overlay control, which is challenging and requires techniques to mitigate these complexities.
Innovation Solution
Incorporating an in-die stitching sub-region with filler cells having a greater critical dimension than the surrounding circuit cells, allowing for in-die stitching without the need for at-resolution precision, thereby relaxing the requirements on alignment and control during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If in-die stitching is performed at EUVL resolution, then image field coverage is improved, but manufacturing precision requirements increase to nanometer-order precision
Solution Approach 1:
The die is divided into multiple image fields that are stitched together, with dedicated stitching sub-regions separated from functional circuit regions. This segmentation allows the stitching process to be isolated to specific areas, reducing the precision requirements for the entire die while maintaining comprehensive coverage.
Solution Approach 2:
Stitching sub-regions act as intermediary zones between separate image fields. These intermediate regions with relaxed critical dimensions serve as buffer zones that accommodate alignment tolerances, preventing the propagation of stitching errors into functional circuit areas.
2Area of stationary object
If in-die stitching is performed at EUVL resolution, then image field coverage is improved, but device complexity increases due to OPC correction requirements
Solution Approach 1:
The device is segmented into functional circuit regions and stitching sub-regions with different design rules. This allows OPC complexity to be concentrated in the stitching sub-regions where relaxed critical dimensions apply, while functional regions maintain their original design simplicity.
Solution Approach 2:
Different critical dimension requirements are applied locally: relaxed critical dimensions in stitching sub-regions and standard critical dimensions in functional circuit regions. This local differentiation reduces overall OPC complexity by applying stringent corrections only where necessary.
3Manufacturing precision
If filler cells with greater critical dimension are used in stitching sub-region, then alignment sensitivity is reduced, but area efficiency decreases
Solution Approach 1:
Stitching sub-regions with filler cells are extracted as separate entities from the functional circuit regions. This extraction isolates the area penalty to non-functional zones, minimizing the impact on overall device area efficiency while achieving reduced alignment sensitivity in critical stitching areas.
Data Source
AI summary
An embodiment includes a method for floorplanning of a circuit region of an IC device which includes: obtaining a floorplan for the circuit region; determining a location of an in-die stitching boundary for the floorplan, the in-die stitching boundary extending in a first direction across the floorplan; placing one or more rows of filler cells in an in-die stitching sub-region of the floorplan, wherein the one or more rows of filler cells extend in the first direction and the in-die stitching sub-region extends along the in-die stitching boundary; and placing in each of a first and a second sub-region of the floorplan on opposite sides of the in-die stitching sub-region, circuit cells in a plurality of rows extending in parallel in the first direction, wherein the filler cells have a critical dimension which is greater than a corresponding critical dimension of the circuit cells of the first and second sub-regions.