Hierarchical IC Floorplanner for Routability and Net Length Optimization
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Solution Overview
Problem
Current IC floorplanning methods often fail to produce suitable routing plans due to inadequate consideration of longer interconnections between modules, leading to suboptimal floorplan solutions, as they primarily focus on shorter nets during the clustering process.
Innovation Solution
A method that initially partitions IC floorspace into regions, allocates modules to minimize net lengths and balance space requirements, then iteratively merges and refines floorplans to reduce net lengths and aspect ratio differences, ensuring all modules are allocated efficiently across the IC area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a top-down hierarchical floorplanner partitions IC floorspace into regions for each module at high level, then the floorplan can be generated quickly, but the placement plan becomes unroutable because routing requirements are not considered
Solution Approach 1:
The patent segments the floorplanning process into multiple hierarchical levels. At each level, the floorspace is partitioned into regions, and modules are allocated to these regions. This segmentation allows the algorithm to consider routing requirements at different granularities, improving routability while maintaining efficiency through the hierarchical structure.
Solution Approach 2:
The patent performs preliminary actions by estimating the size and shape of areas needed for custom modules based on known areas of constituent cells before final placement. This preliminary sizing and shaping of regions ensures that routing requirements are anticipated early in the process, preventing unroutable designs while maintaining quick generation.
2Productivity
If large IP modules are used in large-scale IC designs, then the number of components to be placed is reduced, but the flexibility for placement and routing remaining portions decreases
Solution Approach 1:
The patent applies dynamics by making the floorplanning process adaptive and iterative. The algorithm repeatedly refines the floorplan by adjusting module allocations and region boundaries based on routing feedback. This dynamic refinement allows the system to maintain flexibility even with large IP modules, as the placement can be adjusted iteratively to accommodate routing requirements.
Solution Approach 2:
The patent changes parameters by adjusting the granularity of partitioning at different hierarchical levels. By controlling the maximum number of modules per region and iteratively refining the partitioning, the algorithm can adapt the level of detail to balance the use of large IP modules with the need for placement flexibility, optimizing both productivity and adaptability.
3Device complexity
If the floorplanner focuses on shorter nets during clustering, then the clustering process is simplified, but longer interconnections are inadequately considered leading to suboptimal solutions
Solution Approach 1:
The patent adds another dimension to the clustering process by incorporating hierarchical levels. Instead of focusing solely on short-range clustering, the algorithm performs clustering at multiple scales, from fine-grained local clusters to coarse-grained regional allocations. This multi-dimensional approach ensures long interconnections are considered while keeping the local clustering process manageable.
Solution Approach 2:
The patent performs preliminary estimation of module sizes and region shapes before final placement. This preliminary action allows the algorithm to anticipate the impact of module allocations on both short and long net lengths, enabling better optimization decisions without significantly increasing the complexity of the clustering process itself.
Data Source
AI summary
To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.